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Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references (pages 65-76).

1. Introduction --

2. Historical perspectives of scaled MOSFET evolution --

3. Simulation results of on-state drain current and subthreshold drain current at substrate temperatures below 300 K -- 3.1 Modeling equations to derive on-state drain current as a function of drain voltage for different gate voltages operated at reduced substrate temperatures below 300 K -- 3.1.1 Modeling of substrate or bulk mobility as a function of substrate temperature for 1 [mu]m channel length MOSFET -- 3.1.2 Modeling of drain current as a function of drain voltage for different gate voltage biases at different substrate temperatures -- 3.1.3 Modeling of drain current as a function of substrate temperatures for different gate voltage and drain biases conditions for a long-channel n-MOSFET -- 3.2 Drain current as a function of gate voltage for a fixed low-drain voltage at different substrate temperatures for the 1 [mu]m channel length n-MOSFET [mu]m --

4. Simulation results on substrate mobility and on-channel mobility of conventional long-channel n-MOSFET at substrate temperatures 300 K and below -- 4.1 Electron mobility in p-type substrate of silicon varying with substrate acceptor doping concentrations for different substrate temperatures -- 4.2 Simulation results of electron carrier mobility at the surface of an n-channel MOSFET for different substrate temperatures -- 4.2.1 Modeling equations for extraction of surface mobility as a function of vertical effective field --

5. Simulation outcomes of subthreshold slope factor or coefficient for different substrate temperatures at the vicinity of a subthreshold region to deep subthreshold region of a long-channel n-MOSFET --

6. Review of scaled device architectures for their feasibility to low temperature operation simulation perspectives of the author's current research -- 6.1 Silicon nanowire transistor performance analysis with consideration of low-temperature operation -- 6.2 Negative capacitance ferroelectric Fet (Ncfet) performance analysis with consideration of low-temperature operation --

7. Summary of research results and conclusions -- References -- Author's biography.

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Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book [1] in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.

Also available in print.

Title from PDF title page (viewed on August 1, 2018).