621.395 / R117v
Radecka, Katarzyna
Verification by error modeling : using testing techniques in hardware verification / Katarzyna Radecka and Zeljko Zilic .- Boston: Kluwer Academic Publishers, 2003 .- xiv, 216p . .- ( Frontiers In Electronics Testing / Edited By Vishwani D. Agrawal
ISBN: 9781402076527
Subject Headings:
Integrated circuits;
Very Large Scale Integration;
Computer Aided design;
Author Added Entry:
Zilic, Zeljko;
Copy Details:
Acc. No.: A174930, Full Call No.: 621.395 R117v, Item type: Books , Location: COMPACT STORAGE (BASEMENT),
------------------------- --------------------- ------ --------- ------- ------- --------- --------
Radecka, Katarzyna
Verification by error modeling : using testing techniques in hardware verification / Katarzyna Radecka and Zeljko Zilic .- Boston: Kluwer Academic Publishers, 2003 .- xiv, 216p . .- ( Frontiers In Electronics Testing / Edited By Vishwani D. Agrawal
ISBN: 9781402076527
Subject Headings:
Integrated circuits;
Very Large Scale Integration;
Computer Aided design;
Author Added Entry:
Zilic, Zeljko;
Copy Details:
Acc. No.: A174930, Full Call No.: 621.395 R117v, Item type: Books , Location: COMPACT STORAGE (BASEMENT),
------------------------- --------------------- ------ --------- ------- ------- --------- --------