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Introduction to logic synthesis using Verilog HDL

By: Reese, Robert B. (Robert Bryan) 1958-.
Contributor(s): Thornton, Mitchell Aaron.
Material type: materialTypeLabelBookSeries: Synthesis lectures on digital circuits and systems: #6.Publisher: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2006Edition: 1st ed.Description: 1 electronic text (vii, 75 p. : ill.) : digital file.ISBN: 1598291076 (electronic bk.); 9781598291070 (electronic bk.); 1598291068 (pbk.); 9781598291063 (pbk.).Uniform titles: Synthesis digital library of engineering and computer science. Subject(s): Logic design -- Computer programs | Verilog (Computer hardware description language) | Electronic digital computers -- Design and construction | Computer hardware description languages | Verilog | Digital System Design | Digital Logic Synthesis | HDL (Hardware Description Language) | Combinational Logic | Sequential LogicDDC classification: 621.395 Online resources: Abstract with links to resource | Abstract with links to full text Also available in print.
Contents:
Digital logic review with Verilog quickstart -- Learning objectives -- Logic synthesis introduction and motivation -- Combinational logic in Verilog -- Assign statements -- Always procedural blocks -- Combinational building blocks in Verilog -- Multibit/multiinput muxes, Verilog hierarchical design and bus notation -- Addition, subtraction -- Multiplication, division -- Shifting -- Tri-state logic -- Sequential logic in Verilog -- One-bit storage elements -- DFF chains -- Asynchronous versus synchronous inputs -- Registers, counters, and shift registers -- Event-driven simulation and Verilog -- Event-driven simulation basics -- Timing considerations -- Presynthesis versus postsynthesis simulation -- Blocking versus nonblocking assignments and synthesis -- Verilog coding guidelines -- Summary -- Synchronous sequential circuit design -- Learning objectives -- Sequential circuits -- Sequential circuit motivation -- Synchronizing signals: the clock -- Synchronous sequential circuit architectures -- Contents -- Models of finite state machines -- Basics of algorithmic state machine (ASM) charts -- The ASM chart model and an example controller -- The state diagram model -- State assignment -- Low-level models of controllers -- State equations -- State tables -- Controller circuit analysis -- Mealy and Moore machine conversion -- Mealy to Moore machine conversion -- Moore to Mealy conversion -- State machine equivalence -- Verilog descriptions of synchronous sequential circuits -- Example Verilog descriptions -- Verilog descriptions for the Mealy machine model of an example controller -- Verilog descriptions for the Moore machine model of an example controller -- Summary -- Biography.
Summary: Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.
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Item type Current location Call number Status Date due Barcode Item holds
E books E books PK Kelkar Library, IIT Kanpur
Available EBKE047
Total holds: 0

Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.

Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references (p. 73).

Digital logic review with Verilog quickstart -- Learning objectives -- Logic synthesis introduction and motivation -- Combinational logic in Verilog -- Assign statements -- Always procedural blocks -- Combinational building blocks in Verilog -- Multibit/multiinput muxes, Verilog hierarchical design and bus notation -- Addition, subtraction -- Multiplication, division -- Shifting -- Tri-state logic -- Sequential logic in Verilog -- One-bit storage elements -- DFF chains -- Asynchronous versus synchronous inputs -- Registers, counters, and shift registers -- Event-driven simulation and Verilog -- Event-driven simulation basics -- Timing considerations -- Presynthesis versus postsynthesis simulation -- Blocking versus nonblocking assignments and synthesis -- Verilog coding guidelines -- Summary -- Synchronous sequential circuit design -- Learning objectives -- Sequential circuits -- Sequential circuit motivation -- Synchronizing signals: the clock -- Synchronous sequential circuit architectures -- Contents -- Models of finite state machines -- Basics of algorithmic state machine (ASM) charts -- The ASM chart model and an example controller -- The state diagram model -- State assignment -- Low-level models of controllers -- State equations -- State tables -- Controller circuit analysis -- Mealy and Moore machine conversion -- Mealy to Moore machine conversion -- Moore to Mealy conversion -- State machine equivalence -- Verilog descriptions of synchronous sequential circuits -- Example Verilog descriptions -- Verilog descriptions for the Mealy machine model of an example controller -- Verilog descriptions for the Moore machine model of an example controller -- Summary -- Biography.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.

Also available in print.

Title from PDF t.p. (viewed on October 11, 2008).

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