| 000 -LEADER |
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| fixed length control field |
05381nam a2200661 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6812806 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200413152847.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
|---|
| fixed length control field |
m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
|---|
| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
081011s2006 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
1598291076 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781598291070 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
1598291068 (pbk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781598291063 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00060ED1V01Y200610DCS006 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)73796751 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)gtp00531446 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7868.L6 |
| Item number |
R445 2006 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
22 |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) |
|---|
| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) |
|
| Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) |
MoCl |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Reese, Robert B. |
| Fuller form of name |
(Robert Bryan), |
| Dates associated with a name |
1958- |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Introduction to logic synthesis using Verilog HDL |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Robert B. Reese, Mitchell A. Thornton. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
1st ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool Publishers, |
| Date of publication, distribution, etc. |
c2006. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (vii, 75 p. : ill.) : |
| Other physical details |
digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on digital circuits and systems, |
| International Standard Serial Number |
1932-3174 ; |
| Volume/sequential designation |
#6 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 73). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Digital logic review with Verilog quickstart -- Learning objectives -- Logic synthesis introduction and motivation -- Combinational logic in Verilog -- Assign statements -- Always procedural blocks -- Combinational building blocks in Verilog -- Multibit/multiinput muxes, Verilog hierarchical design and bus notation -- Addition, subtraction -- Multiplication, division -- Shifting -- Tri-state logic -- Sequential logic in Verilog -- One-bit storage elements -- DFF chains -- Asynchronous versus synchronous inputs -- Registers, counters, and shift registers -- Event-driven simulation and Verilog -- Event-driven simulation basics -- Timing considerations -- Presynthesis versus postsynthesis simulation -- Blocking versus nonblocking assignments and synthesis -- Verilog coding guidelines -- Summary -- Synchronous sequential circuit design -- Learning objectives -- Sequential circuits -- Sequential circuit motivation -- Synchronizing signals: the clock -- Synchronous sequential circuit architectures -- Contents -- Models of finite state machines -- Basics of algorithmic state machine (ASM) charts -- The ASM chart model and an example controller -- The state diagram model -- State assignment -- Low-level models of controllers -- State equations -- State tables -- Controller circuit analysis -- Mealy and Moore machine conversion -- Mealy to Moore machine conversion -- Moore to Mealy conversion -- State machine equivalence -- Verilog descriptions of synchronous sequential circuits -- Example Verilog descriptions -- Verilog descriptions for the Mealy machine model of an example controller -- Verilog descriptions for the Moore machine model of an example controller -- Summary -- Biography. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on October 11, 2008). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic design |
| General subdivision |
Computer programs. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic digital computers |
| General subdivision |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer hardware description languages. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Verilog. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Digital System Design. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Digital Logic Synthesis. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
HDL (Hardware Description Language) |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Combinational Logic. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Sequential Logic. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Thornton, Mitchell Aaron. |
| 730 0# - ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on digital circuits and systems ; |
| Volume/sequential designation |
#6. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812806 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to full text |
| Uniform Resource Identifier |
http://dx.doi.org/10.2200/S00060ED1V01Y200610DCS006 |
