Layout techniques for MOSFETS /
By: Gimenez, Salvador Pinillos [author.].
Material type:
BookSeries: Synthesis digital library of engineering and computer science: ; Synthesis lectures on emerging engineering technologies: # 7.Publisher: San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, 2016.Description: 1 PDF (xi, 69 pages) : illustrations.Content type: text Media type: electronic Carrier type: online resourceISBN: 9781627054829.Subject(s): Metal oxide semiconductor field-effect transistors | Integrated circuit layout | layout techniques | Circular Annular MOSFET | pillar surrounding gate MOSFET | Cynthia MOSFET | Diamond MOSFET | Octo MOSFET | Ellipsoidal MOSFET | Fish MOSFET | Wave | MOSFET | LCE | PAMDLE | DEPAMBBRE | DLEFRE | high temperature | Ionizing Radiation Effects | TID and SEEDDC classification: 621.3815284 Online resources: Abstract with links to resource Also available in print.| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
E books
|
PK Kelkar Library, IIT Kanpur | Available | EBKE697 |
Mode of access: World Wide Web.
System requirements: Adobe Acrobat Reader.
Part of: Synthesis digital library of engineering and computer science.
Includes bibliographical references (pages 61-68).
1. Introduction -- 2. The origin of the innovative layout techniques for MOSFETs -- 2.1 Observing and combining different new effects in MOSFETs -- 3. Diamond MOSFET (hexagonal gate geometry) -- 4. Octo layout style (octagonal gate shape) for MOSFET -- 5. Ellipsoidal layout style for MOSFET -- 6. Fish layout style ("<" gate shape) for MOSFET -- 7. Annular circular gate layout style for MOSFET -- 8. Wave layout style ("S" gate shape) for MOSFET -- 9. Conclusions and comments -- References -- About the author.
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
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This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on PN junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
Also available in print.
Title from PDF title page (viewed on April 14, 2016).
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