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Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references (pages 57-61).

1. Introduction -- 1.1 Overview -- 1.2 Host vs. target terminology -- 1.3 Why are fast, accurate simulators of computer targets needed? -- 1.4 Harnessing FPGAs for simulation not prototyping -- 1.5 The rest of the book --

2. Simulator background -- 2.1 Uses of computer simulation -- 2.2 Desired simulator characteristics -- 2.3 Performance simulation accuracy -- 2.4 Simulator design tradeoff -- 2.5 Simulator partitioning for parallelization -- 2.5.1 Spatial partitioning -- 2.5.2 Temporal partitioning -- 2.5.3 Functional/timing partitioning -- 2.5.4 Hybrid partitioning -- 2.6 Functional/timing simulation architectures -- 2.6.1 Monolithic simulators -- 2.6.2 Timing-directed simulators -- 2.6.3 Functional-first simulators -- 2.6.4 Timing-first simulators -- 2.6.5 Speculative functional-first -- 2.7 Simulation events and synchronization -- 2.7.1 Centralized synchronization -- 2.7.2 Decentralized event synchronization --

3. Accelerating computer system simulators with FPGAs -- 3.1 Exploiting target partitioning on FPGAs -- 3.2 Accelerating traditional simulator architectures with FPGAs -- 3.2.1 Accelerating monolithic simulators with FPGAs -- 3.2.2 Accelerating timing-directed simulators with FPGAs -- 3.2.3 Accelerating functional-first simulators with FPGAs -- 3.2.4 Accelerating timing-first simulators with FPGAs -- 3.2.5 Accelerating speculative functional-first with FPGAs -- 3.2.6 Accelerating combined simulator architectures with FPGAs -- 3.3 Managing time through simulation event sychronization in an FPGA-accelerated simulator -- 3.3.1 Centralized barrier synchronization in an FPGA-accelerated simulator -- 3.3.2 Decentralized barrier synchronization in an FPGA-accelerated simulator -- 3.4 FPGA simulator programmability -- 3.5 Case study: FPGA-accelerated simulation technologies (FAST) --

4. Simulation virtualization -- 4.1 Full-system and multiprocessor simulation -- 4.2 Hierarchical simulation with transplanting -- 4.2.1 Hierarchical simulation -- 4.2.2 Transplanting -- 4.2.3 Hierarchical transplanting -- 4.3 Virtualized simulation of multiprocessors -- 4.3.1 Time-multiplexed virtualization -- 4.3.2 Virtualizing memory capacity -- 4.4 Case study: the Protoflex simulator -- 4.4.1 ProtoFlex design overview -- 4.4.2 BlueSPARC pipeline -- 4.4.3 Performance evaluation -- 4.4.4 Hierarchical simulation and virtualization in a performance simulator --

5. Categorizing FPGA-based simulators -- 5.1 Fame classifications -- 5.2 Open-sourced FPGA-based simulators -- 5.2.1 ProtoFlex -- 5.2.2 HAsim -- 5.2.3 RAMP Gold --

6. Conclusion -- A. Field programmable gate arrays -- Programmable logic elements -- Embedded SRAM blocks -- Hard "macros" -- Bibliography -- Authors' biographies.

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To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of the- art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques.

Also available in print.

Title from PDF title page (viewed on September 18, 2014).