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FPGA-accelerated simulation of computer systems / (Record no. 562085)

000 -LEADER
fixed length control field 06134nam a2200721 i 4500
001 - CONTROL NUMBER
control field 6894333
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200413152915.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m eo d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr cn |||m|||a
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 140918s2014 caua foab 000 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781627052146
Qualifying information ebook
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781627052139
Qualifying information print
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.2200/S00586ED1V01Y201407CAC029
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)swl00403921
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)890973752
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Language of cataloging eng
Description conventions rda
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7895.G36
Item number A533 2014
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Edition number 23
090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN)
Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR)
Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) MoCl
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Angepat, Hari.,
Relator term author.
245 10 - TITLE STATEMENT
Title FPGA-accelerated simulation of computer systems /
Statement of responsibility, etc. Hari Angepat, Derek Chiou, Eric S. Chung, James C. Hoe.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) :
Name of producer, publisher, distributor, manufacturer Morgan & Claypool,
Date of production, publication, distribution, manufacture, or copyright notice 2014.
300 ## - PHYSICAL DESCRIPTION
Extent 1 PDF (xv, 64 pages) :
Other physical details illustrations.
336 ## - CONTENT TYPE
Content type term text
Source rdacontent
337 ## - MEDIA TYPE
Media type term electronic
Source isbdmedia
338 ## - CARRIER TYPE
Carrier type term online resource
Source rdacarrier
490 1# - SERIES STATEMENT
Series statement Synthesis lectures on computer architecture,
International Standard Serial Number 1935-3243 ;
Volume/sequential designation # 29
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web.
538 ## - SYSTEM DETAILS NOTE
System details note System requirements: Adobe Acrobat Reader.
500 ## - GENERAL NOTE
General note Part of: Synthesis digital library of engineering and computer science.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references (pages 57-61).
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1. Introduction -- 1.1 Overview -- 1.2 Host vs. target terminology -- 1.3 Why are fast, accurate simulators of computer targets needed? -- 1.4 Harnessing FPGAs for simulation not prototyping -- 1.5 The rest of the book --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 2. Simulator background -- 2.1 Uses of computer simulation -- 2.2 Desired simulator characteristics -- 2.3 Performance simulation accuracy -- 2.4 Simulator design tradeoff -- 2.5 Simulator partitioning for parallelization -- 2.5.1 Spatial partitioning -- 2.5.2 Temporal partitioning -- 2.5.3 Functional/timing partitioning -- 2.5.4 Hybrid partitioning -- 2.6 Functional/timing simulation architectures -- 2.6.1 Monolithic simulators -- 2.6.2 Timing-directed simulators -- 2.6.3 Functional-first simulators -- 2.6.4 Timing-first simulators -- 2.6.5 Speculative functional-first -- 2.7 Simulation events and synchronization -- 2.7.1 Centralized synchronization -- 2.7.2 Decentralized event synchronization --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3. Accelerating computer system simulators with FPGAs -- 3.1 Exploiting target partitioning on FPGAs -- 3.2 Accelerating traditional simulator architectures with FPGAs -- 3.2.1 Accelerating monolithic simulators with FPGAs -- 3.2.2 Accelerating timing-directed simulators with FPGAs -- 3.2.3 Accelerating functional-first simulators with FPGAs -- 3.2.4 Accelerating timing-first simulators with FPGAs -- 3.2.5 Accelerating speculative functional-first with FPGAs -- 3.2.6 Accelerating combined simulator architectures with FPGAs -- 3.3 Managing time through simulation event sychronization in an FPGA-accelerated simulator -- 3.3.1 Centralized barrier synchronization in an FPGA-accelerated simulator -- 3.3.2 Decentralized barrier synchronization in an FPGA-accelerated simulator -- 3.4 FPGA simulator programmability -- 3.5 Case study: FPGA-accelerated simulation technologies (FAST) --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 4. Simulation virtualization -- 4.1 Full-system and multiprocessor simulation -- 4.2 Hierarchical simulation with transplanting -- 4.2.1 Hierarchical simulation -- 4.2.2 Transplanting -- 4.2.3 Hierarchical transplanting -- 4.3 Virtualized simulation of multiprocessors -- 4.3.1 Time-multiplexed virtualization -- 4.3.2 Virtualizing memory capacity -- 4.4 Case study: the Protoflex simulator -- 4.4.1 ProtoFlex design overview -- 4.4.2 BlueSPARC pipeline -- 4.4.3 Performance evaluation -- 4.4.4 Hierarchical simulation and virtualization in a performance simulator --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 5. Categorizing FPGA-based simulators -- 5.1 Fame classifications -- 5.2 Open-sourced FPGA-based simulators -- 5.2.1 ProtoFlex -- 5.2.2 HAsim -- 5.2.3 RAMP Gold --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 6. Conclusion -- A. Field programmable gate arrays -- Programmable logic elements -- Embedded SRAM blocks -- Hard "macros" -- Bibliography -- Authors' biographies.
506 1# - RESTRICTIONS ON ACCESS NOTE
Terms governing access Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0# - CITATION/REFERENCES NOTE
Name of source Compendex
510 0# - CITATION/REFERENCES NOTE
Name of source INSPEC
510 0# - CITATION/REFERENCES NOTE
Name of source Google scholar
510 0# - CITATION/REFERENCES NOTE
Name of source Google book search
520 3# - SUMMARY, ETC.
Summary, etc. To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of the- art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Title from PDF title page (viewed on September 18, 2014).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Field programmable gate arrays.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer systems
General subdivision Computer simulation.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer simulation.
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term simulation
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term cycle-accurate
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term functional
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term timing
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term FPGA accelerated
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Chiou, Derek.,
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Chung, Eric S.,
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Hoe, James C.,
Relator term author.
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Print version:
International Standard Book Number 9781627052139
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis digital library of engineering and computer science.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis lectures in computer architecture ;
Volume/sequential designation # 29.
International Standard Serial Number 1935-3243
856 40 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to full text
Uniform Resource Identifier http://dx.doi.org/10.2200/S00586ED1V01Y201407CAC029
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier http://ieeexplore.ieee.org/servlet/opac?bknumber=6894333
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Barcode Date last seen Price effective from Koha item type
        PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2020-04-13 EBKE585 2020-04-13 2020-04-13 E books

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