Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.

Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references (pages 77-90).

List of figures -- List of tables -- List of acronyms -- Acknowledgments -- 1. Introduction -- 1.1 Organization of the lecture --

2. Photonic interconnect basics -- 2.1 Transmitter -- 2.1.1 Lasers -- 2.1.2 Microring resonators -- 2.1.3 Microrings as modulators -- 2.2 Transmission medium -- 2.2.1 Waveguide details -- 2.2.2 Vias -- 2.3 Receiver -- 2.3.1 Photodetector details --

3. Link construction -- 3.1 Photonic link design -- 3.1.1 Transmitter -- 3.1.2 Transmission medium -- 3.1.3 Receiver -- 3.1.4 Design decisions -- 3.1.5 Photonic power requirements -- 3.1.6 Electronic power requirements -- 3.1.7 Layout/implementation issues -- 3.1.8 Wide and slow or narrow and fast? -- 3.1.9 Total power --

4. On-chip photonic networks -- 4.1 Photonic network design challenges -- 4.1.1 Buffering -- 4.1.2 Topology -- 4.1.3 Arbitration and flow control -- 4.1.4 Electrical/optical codesign -- 4.1.5 Latency -- 4.2 Case studies of on-chip photonic networks -- 4.2.1 Corona -- 4.2.2 Phastlane -- 4.2.3 Firefly -- 4.2.4 Flexishare -- 4.2.5 DCAF -- 4.2.6 Hybrid photonic NoC --

5. Challenges -- 5.1 Process variations -- 5.2 Thermal issues -- 5.3 Trimming -- 5.4 Resilient on-chip photonic networks -- 5.4.1 Photonic link fault models -- 5.4.2 Link component structure-dependent errors -- 5.4.3 Unidirectional bit errors -- 5.4.4 Mean time between failures --

6. Other developments -- 6.1 On-chip network developments -- 6.1.1 Monolithic CMOS integration -- 6.1.2 Lasers -- 6.1.3 Plasmonics -- 6.2 System-level developments -- 6.2.1 Off-chip I/O -- 6.2.2 Memory system -- 6.2.3 Large-scale routers --

7. Summary & conclusion -- 7.1 Observations and things to remember -- Bibliography -- Authors' biographies.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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As the number of cores on a chip continues to climb, architects will need to address both band-width and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks.

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Title from PDF title page (viewed on November 13, 2013).