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On-chip photonic interconnects : (Record no. 562034)

000 -LEADER
fixed length control field 05455nam a2200733 i 4500
001 - CONTROL NUMBER
control field 6812848
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200413152912.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m eo d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr cn |||m|||a
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 131113s2014 caua foab 000 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781627052122
Qualifying information ebook
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781627052115
Qualifying information paperback
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.2200/S00537ED1V01Y201309CAC027
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)swl00402945
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)862937555
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Language of cataloging eng
Description conventions rda
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7874.53
Item number .N576 2014
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN)
Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR)
Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) MoCl
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Nitta, Christopher J.,
Relator term author.
245 10 - TITLE STATEMENT
Title On-chip photonic interconnects :
Remainder of title a computer architect's perspective /
Statement of responsibility, etc. Christopher J. Nitta, Matthew K. Farrens, and Venkatesh Akella.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) :
Name of producer, publisher, distributor, manufacturer Morgan & Claypool,
Date of production, publication, distribution, manufacture, or copyright notice 2014.
300 ## - PHYSICAL DESCRIPTION
Extent 1 PDF (xix, 91 pages) :
Other physical details illustrations.
336 ## - CONTENT TYPE
Content type term text
Source rdacontent
337 ## - MEDIA TYPE
Media type term electronic
Source isbdmedia
338 ## - CARRIER TYPE
Carrier type term online resource
Source rdacarrier
490 1# - SERIES STATEMENT
Series statement Synthesis lectures on computer architecture,
International Standard Serial Number 1935-3243 ;
Volume/sequential designation # 27
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web.
538 ## - SYSTEM DETAILS NOTE
System details note System requirements: Adobe Acrobat Reader.
500 ## - GENERAL NOTE
General note Part of: Synthesis digital library of engineering and computer science.
500 ## - GENERAL NOTE
General note Series from website.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references (pages 77-90).
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note List of figures -- List of tables -- List of acronyms -- Acknowledgments -- 1. Introduction -- 1.1 Organization of the lecture --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 2. Photonic interconnect basics -- 2.1 Transmitter -- 2.1.1 Lasers -- 2.1.2 Microring resonators -- 2.1.3 Microrings as modulators -- 2.2 Transmission medium -- 2.2.1 Waveguide details -- 2.2.2 Vias -- 2.3 Receiver -- 2.3.1 Photodetector details --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3. Link construction -- 3.1 Photonic link design -- 3.1.1 Transmitter -- 3.1.2 Transmission medium -- 3.1.3 Receiver -- 3.1.4 Design decisions -- 3.1.5 Photonic power requirements -- 3.1.6 Electronic power requirements -- 3.1.7 Layout/implementation issues -- 3.1.8 Wide and slow or narrow and fast? -- 3.1.9 Total power --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 4. On-chip photonic networks -- 4.1 Photonic network design challenges -- 4.1.1 Buffering -- 4.1.2 Topology -- 4.1.3 Arbitration and flow control -- 4.1.4 Electrical/optical codesign -- 4.1.5 Latency -- 4.2 Case studies of on-chip photonic networks -- 4.2.1 Corona -- 4.2.2 Phastlane -- 4.2.3 Firefly -- 4.2.4 Flexishare -- 4.2.5 DCAF -- 4.2.6 Hybrid photonic NoC --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 5. Challenges -- 5.1 Process variations -- 5.2 Thermal issues -- 5.3 Trimming -- 5.4 Resilient on-chip photonic networks -- 5.4.1 Photonic link fault models -- 5.4.2 Link component structure-dependent errors -- 5.4.3 Unidirectional bit errors -- 5.4.4 Mean time between failures --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 6. Other developments -- 6.1 On-chip network developments -- 6.1.1 Monolithic CMOS integration -- 6.1.2 Lasers -- 6.1.3 Plasmonics -- 6.2 System-level developments -- 6.2.1 Off-chip I/O -- 6.2.2 Memory system -- 6.2.3 Large-scale routers --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 7. Summary & conclusion -- 7.1 Observations and things to remember -- Bibliography -- Authors' biographies.
506 1# - RESTRICTIONS ON ACCESS NOTE
Terms governing access Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0# - CITATION/REFERENCES NOTE
Name of source Compendex
510 0# - CITATION/REFERENCES NOTE
Name of source INSPEC
510 0# - CITATION/REFERENCES NOTE
Name of source Google scholar
510 0# - CITATION/REFERENCES NOTE
Name of source Google book search
520 3# - SUMMARY, ETC.
Summary, etc. As the number of cores on a chip continues to climb, architects will need to address both band-width and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Title from PDF title page (viewed on November 13, 2013).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Interconnects (Integrated circuit technology)
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Nanophotonics.
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term nanophotonics
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term on-chip network
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term interconnect
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term microring
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term optical interconnects
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term network topologies
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Farrens, Matthew K.,
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Akella, Venkatesh,
Dates associated with a name 1982-,
Relator term author.
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Print version:
International Standard Book Number 9781627052115
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis digital library of engineering and computer science.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis lectures in computer architecture ;
Volume/sequential designation # 27.
International Standard Serial Number 1935-3243
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier http://ieeexplore.ieee.org/servlet/opac?bknumber=6812848
856 40 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to full text
Uniform Resource Identifier http://dx.doi.org/10.2200/S00537ED1V01Y201309CAC027
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Barcode Date last seen Price effective from Koha item type
        PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2020-04-13 EBKE534 2020-04-13 2020-04-13 E books

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