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An introduction to logic circuit testing

By: Lala, Parag K 1948-.
Material type: materialTypeLabelBookSeries: Synthesis lectures on digital circuits and systems: # 17.Publisher: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009Description: 1 electronic text (x, 99 p. : ill.) : digital file.ISBN: 9781598293517 (electronic bk.); 9781598293500 (pbk.).Uniform titles: Synthesis digital library of engineering and computer science. Subject(s): Logic circuits -- Testing | Digital electronics -- Testing | Integrated circuits -- Very large scale integration -- Testing | Digital circuits | Logic circuit testing | VLSI | Fault detection | Design-for-testability | Response evaluation techniques | BIST | D-Algorithm | PODEM | FAN | LFSRDDC classification: 621.395 Online resources: Abstract with links to resource Also available in print.
Contents:
Introduction -- Faults in logic circuits -- Stuck-at fault -- Bridging faults -- Delay fault -- Breaks and transistors stuck-open and stuck-on or stuck-open faults in CMOS -- Breaks -- Stuck-on and stuck-open faults -- Basic concepts of fault detection -- Controllability and observability -- Undetectable faults -- Equivalent faults -- Temporary faults -- References -- Fault detection in logic circuits -- Test generation for combinational logic circuits -- Truth table and fault matrix -- Path sensitization -- D-algorithm -- PODEM -- FAN -- Delay fault detection -- Testing of sequential circuits -- Designing checking experiments -- Test generation using the circuit structure and the state table -- References -- Design for testability -- Ad hoc techniques -- Scan-path technique for testable sequential circuit design -- Level-sensitive scan design -- Clocked hazard-free latches -- Double-latch and single-latch LSSD -- Random access scan technique -- Partial scan -- Testable sequential circuit design using nonscan techniques -- Crosscheck -- Boundary scan -- References -- Built-in self-test -- Test pattern generation for BIST -- Exhaustive testing -- Pseudoexhaustive pattern generation -- Pseudorandom pattern generator -- Deterministic testing -- Output response analysis -- Transition count -- Syndrome checking -- Signature analysis -- BIST architectures -- Built-in logic block observer -- Self-testing using an MISR and parallel shift register sequence generator -- LSSD on-chip self-test.
Summary: An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips.
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Item type Current location Call number Status Date due Barcode Item holds
E books E books PK Kelkar Library, IIT Kanpur
Available EBKE143
Total holds: 0

Mode of access: World Wide Web.

System requirements: Adobe Acrobat reader.

Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references.

Introduction -- Faults in logic circuits -- Stuck-at fault -- Bridging faults -- Delay fault -- Breaks and transistors stuck-open and stuck-on or stuck-open faults in CMOS -- Breaks -- Stuck-on and stuck-open faults -- Basic concepts of fault detection -- Controllability and observability -- Undetectable faults -- Equivalent faults -- Temporary faults -- References -- Fault detection in logic circuits -- Test generation for combinational logic circuits -- Truth table and fault matrix -- Path sensitization -- D-algorithm -- PODEM -- FAN -- Delay fault detection -- Testing of sequential circuits -- Designing checking experiments -- Test generation using the circuit structure and the state table -- References -- Design for testability -- Ad hoc techniques -- Scan-path technique for testable sequential circuit design -- Level-sensitive scan design -- Clocked hazard-free latches -- Double-latch and single-latch LSSD -- Random access scan technique -- Partial scan -- Testable sequential circuit design using nonscan techniques -- Crosscheck -- Boundary scan -- References -- Built-in self-test -- Test pattern generation for BIST -- Exhaustive testing -- Pseudoexhaustive pattern generation -- Pseudorandom pattern generator -- Deterministic testing -- Output response analysis -- Transition count -- Syndrome checking -- Signature analysis -- BIST architectures -- Built-in logic block observer -- Self-testing using an MISR and parallel shift register sequence generator -- LSSD on-chip self-test.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips.

Also available in print.

Title from PDF t.p. (viewed on December 3, 2008).

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