Finite state machine datapath design, optimization, and implementation
By: Davis, Justin S.
Contributor(s): Reese, Robert B.
Material type:
BookSeries: Synthesis lectures on digital circuits and systems: #14.Publisher: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2008Description: 1 electronic text (ix, 113 p. : ill.) : digital file.ISBN: 1598295306 (electronic bk.); 9781598295306 (electronic bk.); 1598295292 (pbk.); 9781598295290 (pbk.).Uniform titles: Synthesis digital library of engineering and computer science. Subject(s): Electronic digital computers -- Design and construction | Verilog | Datapath | Scheduling | Latency | Throughput | Timing | Pipelining | Memories | FPGA | FlowgraphDDC classification: 621.3916 Online resources: Abstract with links to resource | Abstract with links to full text Also available in print.| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
E books
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PK Kelkar Library, IIT Kanpur | Available | EBKE045 |
Mode of access: World Wide Web.
System requirements: Adobe Acrobat Reader.
Part of: Synthesis digital library of engineering and computer science.
Series from website.
Includes bibliographical references.
Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs.
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
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Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
Also available in print.
Title from PDF t.p. (viewed on October 11, 2008).
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