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Finite state machine datapath design, optimization, and implementation (Record no. 561545)

000 -LEADER
fixed length control field 03989nam a2200661 i 4500
001 - CONTROL NUMBER
control field 6812910
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200413152847.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m eo d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr cn |||m|||a
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 081011s2008 caua foab 000 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 1598295306 (electronic bk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781598295306 (electronic bk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 1598295292 (pbk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781598295290 (pbk.)
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.2200/S00087ED1V01Y200702DCS014
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)186658091
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)gtp00531444
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.3
Item number .D284 2008
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3916
Edition number 22
090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN)
Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR)
Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) MoCl
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Davis, Justin S.,
Dates associated with a name 1975-
245 10 - TITLE STATEMENT
Title Finite state machine datapath design, optimization, and implementation
Medium [electronic resource] /
Statement of responsibility, etc. Justin Davis, Robert Reese.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Name of publisher, distributor, etc. Morgan & Claypool Publishers,
Date of publication, distribution, etc. c2008.
300 ## - PHYSICAL DESCRIPTION
Extent 1 electronic text (ix, 113 p. : ill.) :
Other physical details digital file.
490 1# - SERIES STATEMENT
Series statement Synthesis lectures on digital circuits and systems,
International Standard Serial Number 1932-3174 ;
Volume/sequential designation #14
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web.
538 ## - SYSTEM DETAILS NOTE
System details note System requirements: Adobe Acrobat Reader.
500 ## - GENERAL NOTE
General note Part of: Synthesis digital library of engineering and computer science.
500 ## - GENERAL NOTE
General note Series from website.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs.
506 1# - RESTRICTIONS ON ACCESS NOTE
Terms governing access Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0# - CITATION/REFERENCES NOTE
Name of source Compendex
510 0# - CITATION/REFERENCES NOTE
Name of source INSPEC
510 0# - CITATION/REFERENCES NOTE
Name of source Google scholar
510 0# - CITATION/REFERENCES NOTE
Name of source Google book search
520 ## - SUMMARY, ETC.
Summary, etc. Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Title from PDF t.p. (viewed on October 11, 2008).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic digital computers
General subdivision Design and construction.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Verilog.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Datapath.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Scheduling.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Latency.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Throughput.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Timing.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Pipelining.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Memories.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element FPGA.
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Flowgraph.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Reese, Robert B.
Fuller form of name (Robert Bryan),
Dates associated with a name 1958-
730 0# - ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis digital library of engineering and computer science.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis lectures on digital circuits and systems ;
Volume/sequential designation #14.
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier http://ieeexplore.ieee.org/servlet/opac?bknumber=6812910
856 40 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to full text
Uniform Resource Identifier http://dx.doi.org/10.2200/S00087ED1V01Y200702DCS014
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Barcode Date last seen Price effective from Koha item type
        PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2020-04-13 EBKE045 2020-04-13 2020-04-13 E books

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