DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS
By: Sachdev,Manoj,Gyvez,Jose Pineda De.
Contributor(s): Agarwal,Vishwani D.
Material type:![materialTypeLabel](/opac-tmpl/lib/famfamfam/BK.png)
Item type | Current location | Collection | Call number | url | Status | Date due | Barcode | Item holds |
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PK Kelkar Library, IIT Kanpur | COMPACT STORAGE (BASEMENT) | 621.3815 SA14D2 (Browse shelf) | Book Request | Available | A159498 |
Total holds: 0
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621.3815 R913m MODULATION AND CODING IN INFORMATION SYSTEMS | 621.3815 R913m MODULATION AND CODING IN INFORMATION SYSTEMS | 621.3815 R913m MODULATION AND CODING IN INFORMATION SYSTEMS | 621.3815 SA14D2 DEFECT-ORIENTED TESTING FOR NANO-METRIC CMOS VLSI CIRCUITS | 621.3815 Sa97i Invention of integrated circuits | 621.3815 Sch95s SELECTED SEMICONDUCTOR CIRCUITS HANDBOOK | 621.3815 Se42s SEMICONDUCTOR FUNDAMENTALS |
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