| 000 -LEADER |
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| fixed length control field |
05965nam a2200565 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6812992 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200413152855.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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| fixed length control field |
m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
090809s2009 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781598295856 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781598295849 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00209ED1V01Y200907CAC008 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)gtp00535456 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)428595223 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK5105.546 |
| Item number |
.E575 2009 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.1 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Enright Jerger, Natalie D. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
On-chip networks |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Natalie Enright Jerger, Li-Shiuan Peh. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool Publishers, |
| Date of publication, distribution, etc. |
c2009. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xii, 127 p. : ill.) : |
| Other physical details |
digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 8 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 105-125). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction -- The advent of the multi-core era -- Communication demands of multi-core architectures -- On-chip vs. off-chip networks -- Network basics: a quick primer -- Evolution to on-chip networks -- On-chip network building blocks -- Performance and cost -- Commercial on-chip network chips -- This book -- Interface with system architecture -- Shared memory networks in chip multiprocessors -- Impact of coherence protocol on network performance -- Coherence protocol requirements for the on-chip network -- Protocol-level network deadlock -- Impact of cache hierarchy implementation on network performance -- Home node and memory controller design issues -- Miss and transaction status holding registers -- Synthesized NoCs in MPSoCs -- The role of application characterization in NoC design -- Design requirements for on-chip network -- NoC synthesis -- NoC network interface standards -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Topology -- Metrics for comparing topologies -- Direct topologies: rings, meshes and Tori -- Indirect topologies: butterflies, Clos networks and fat trees -- Irregular topologies -- Splitting and merging -- Topology synthesis algorithm example -- Layout and implementation -- Concentrators -- Implication of abstract metrics on on-chip implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Routing -- Types of routing algorithms -- Deadlock avoidance -- Deterministic dimension-ordered routing -- Oblivious routing -- Adaptive routing -- Adaptive turn model routing -- Implementation -- Source routing -- Node table-based routing -- Combinational circuits -- Adaptive routing -- Routing on irregular topologies -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Flow control -- Messages, packets, flits and phits -- Message-based flow control -- Circuit switching -- Packet-based flow control -- Store and forward -- Cut-through -- Flit-based flow control -- Wormhole -- Virtual channels -- Deadlock-free flow control -- Escape VCs -- Buffer backpressure -- Implementation -- Buffer sizing for turnaround time -- Reverse signaling wires -- Flow control implementation in MPSoCs -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Router microarchitecture -- Virtual channel router microarchitecture -- Pipeline -- Pipeline implementation -- Pipeline optimizations -- Buffer organization -- Switch design -- Crossbar designs -- Crossbar speedup -- Crossbar slicing -- Allocators and arbiters -- Round-robin arbiter -- Matrix arbiter -- Separable allocator -- Wavefront allocator -- Allocator organization -- Implementation -- Router floorplanning -- Buffer implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Conclusions -- Gap between state-of-the-art and ideal -- Definition of ideal interconnect fabric -- Definition of state-of-the-art -- Network power-delay-throughput gap -- Key research challenges -- Low-power on-chip networks -- Beyond conventional interconnects -- Resilient on-chip networks -- NoC infrastructures -- On-chip network benchmarks -- On-chip networks conferences -- Bibliographic notes. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on August 9, 2009). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Networks on a chip. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Interconnection networks |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Topology |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Routing |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Flow control |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Computer architecture |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Multiprocessor system on chip |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Peh, Li-Shiuan. |
| 730 0# - ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 8. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812992 |
