000			01925 a2200241 4500
003			OSt
020			_a9783319123707
040			_cIIT Kanpur
041			_aeng
082			_a005.82 _bR241t
100			_aRebeiro, Chester
245			_aTiming channels in cryptography [Perpetual access] _ba micro-architectural perspective _cChester Rebeiro, Debdeep Mukhopadhyay and Sarani Bhattacharya
260			_bSpringer _c2015 _aSwitzerland
300			_axvii, 152p
520			_aThis book deals with timing attacks on software implementations of encryption algorithms. It describes and analyzes various unintended covert timing channels that are formed when ciphers are executed in microprocessors. Modern superscalar microprocessors are considered, which are enabled with features such as multi-threaded, pipelined, parallel, speculative, and out-of-order execution. Various timing attack algorithms are described and analyzed for block ciphers as well as public-key ciphers. The interplay between the cipher implementation, system architecture, and the attack's success is analyzed. Further hardware and software countermeasures are discussed with the aim of illustrating methods to build systems that can protect against these attacks. Discusses various timing attack algorithms in detail allowing readers to reconstruct the attack. Provides several experimental results to support the theoretical analysis provided in the book. Analyzes information leakage from cache memories and branch prediction units in the processor. Examines information leakage models that would help quantify leakage in a covert timing channels.
650			_aData encryption (Computer science)
650			_aData structures (Computer science)
650			_aCryptography
700			_aMukhopadhyay, Debdeep
700			_aBhattacharya, Sarani
856			_uhttps://link.springer.com/book/10.1007%2F978-3-319-12370-7#about
942			_cEBK
999			_c565145 _d565145