000 06487nam a2200961 i 4500
001 8886870
003 IEEE
005 20200413152934.0
006 m eo d
007 cr bn |||m|||a
008 191030s2019 caua ob 001 0 eng d
020 _a9781681736761
_qelectronic
020 _z9781681736778
_qhardcover
020 _z9781681736754
_qpaperback
024 7 _a10.2200/S00953ED1V01Y201909DCS057
_2doi
035 _a(CaBNVSL)thg00979616
035 _a(OCoLC)1125959204
040 _aCaBNVSL
_beng
_erda
_cCaBNVSL
_dCaBNVSL
050 4 _aTK7895.M4
_bS375 2019eb
082 0 4 _a004.5
_223
100 1 _aSasao, Tsutomu,
_d1950-
_eauthor.
245 1 0 _aIndex generation functions /
_cTsutomu Sasao.
264 1 _a[San Rafael, California] :
_bMorgan & Claypool,
_c[2019]
300 _a1 PDF (xvii, 165 pages) :
_billustrations.
336 _atext
_2rdacontent
337 _aelectronic
_2isbdmedia
338 _aonline resource
_2rdacarrier
490 1 _aSynthesis lectures on digital circuits and systems,
_x1932-3174 ;
_v#57
538 _aMode of access: World Wide Web.
538 _aSystem requirements: Adobe Acrobat Reader.
500 _aPart of: Synthesis digital library of engineering and computer science.
504 _aIncludes bibliographical references (pages 153-160) and index.
505 8 _a12. References on index generation functions -- 12.1. Reduction of variables -- 12.2. Realization with multiple IGUs -- 12.3. Decomposition -- 12.4. Analysis -- 12.5. Architecture -- 12.6. Applications -- 12.7. Survey -- 12.8. Miscellaneous -- 13. Conclusions.
505 0 _a1. Introduction -- 1.1. Motivation -- 1.2. Organization of the book
505 8 _a2. Applications -- 2.1. IP address table -- 2.2. Terminal access controller -- 2.3. URL list -- 2.4. Computer virus scanning circuit -- 2.5. Memory patch circuit -- 2.6. List of English words -- 2.7. Code converter -- 2.8. Remarks
505 8 _a3. Definitions and basic properties -- 3.1. Logic functions -- 3.2. Functional decomposition -- 3.3. Symmetric functions -- 3.4. Linear functions -- 3.5. Constant-weight code -- 3.6. Euler’s number e and its property -- 3.7. Remarks -- 3.8. Exercises
505 8 _a4. Index generation functions and their realizations -- 4.1. Index generation function -- 4.2. LUT cascade realization -- 4.3. Index generation unit (IGU) -- 4.4 Remarks -- 4.5. Exercises
505 8 _a5. Minimization of primitive variables -- 5.1. Minimization algorithm -- 5.2. Detection of essential variables -- 5.3. Random index generation functions -- 5.4. Remarks -- 5.5. Exercises
505 8 _a6. Linear transformations of input variables -- 6.1. Linear decomposition -- 6.2. Reduction by linear transformations -- 6.3. Heuristic method to find linear transformations -- 6.4. Experimental results -- 6.5. Remarks -- 6.6. Exercises
505 8 _a7. Iterative reduction of compound variables -- 7.1. Improved upper bound -- 7.2. Illustrative examples -- 7.3. Iterative method to reduce compound variables -- 7.4. Comparison of minimization methods -- 7.5. Remarks -- 7.6. Exercises
505 8 _a8. Irreducible index generation function -- 8.1. Irreducible index generation function -- 8.2. Minimum-weight irreducible index generation functions -- 8.3. Normal minimum-weight irreducible index generation functions -- 8.4. Remarks -- 8.5. Exercises
505 8 _a9. SAT-based method to find linear transformations -- 9.1. Sat-based formulation -- 9.2. Reduction of search space for general functions -- 9.3. Reduction of search space for cf-symmetric functions -- 9.4. Experimental results -- 9.5. Remarks -- 9.6. Exercises
505 8 _a10. Statistical approach -- 10.1. Hash function -- 10.2. Number of vectors realized by main memory -- 10.3. Hybrid method -- 10.4. Super hybrid method -- 10.5. Parallel sieve method -- 10.6. Remarks -- 10.7. Exercises
505 8 _a11. Realization using four IGUs -- 11.1. Realization using four IGUs -- 11.2. Selection of linear transformations -- 11.3. Experimental results -- 11.4. Remarks
506 _aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 _aCompendex
510 0 _aINSPEC
510 0 _aGoogle scholar
510 0 _aGoogle book search
520 _aIndex generation functions are binary-input integer valued functions. They represent functions of content addressable memories (CAMs). Applications include: IP address tables; terminal controllers; URL lists; computer virus scanning circuits; memory patch circuits; list of English words; code converters; and pattern matching circuits. This book shows memory-based realization of index generation functions. It shows: 1. methods to implement index generation functions by look-up table (LUT) cascades and index generation units (IGU), 2. methods to reduce the number of variables using linear transformations, and 3. methods to estimate the sizes of memories, with many illustrations, tables, examples, exercises, and their solutions.
530 _aAlso available in print.
588 _aTitle from PDF title page (viewed on October 27, 2019).
650 0 _aAssociative storage.
650 0 _aSubroutines (Computer programs)
650 0 _aVariables (Mathematics)
653 _aaffine equivalence
653 _acode converter
653 _aconstant-weight code
653 _acomputer virus scanning
653 _aequivalence class
653 _afunctional decomposition
653 _ahash function
653 _aincompletely specified function
653 _aindex generation function
653 _aindex generation unit
653 _aIP address table
653 _airreducible index generation function
653 _alinear decomposition
653 _alinear transformation
653 _aLUT cascade
653 _aminimization of variables
653 _am-out-of-n code
653 _arandom function
653 _aSAT solver
653 _asymmetric function
653 _aupper bound
653 _aURL list
776 0 8 _iPrint version:
_z9781681736778
_z9781681736754
830 0 _aSynthesis digital library of engineering and computer science.
830 0 _aSynthesis lectures on digital circuits and systems ;
_v#57.
856 4 0 _3Abstract with links to full text
_uhttps://doi.org/10.2200/S00953ED1V01Y201909DCS057
856 4 2 _3Abstract with links to resource
_uhttps://ieeexplore.ieee.org/servlet/opac?bknumber=8886870
999 _c562446
_d562446