000 04543nam a2200733 i 4500
001 7446015
003 IEEE
005 20200413152921.0
006 m eo d
007 cr cn |||m|||a
008 160414s2016 caua foab 000 0 eng d
020 _a9781627054829
_qebook
020 _z9781627054881
_qprint
024 7 _a10.2200/S00704ED1V01Y201602EET007
_2doi
035 _a(CaBNVSL)swl00406396
035 _a(OCoLC)946774746
040 _aCaBNVSL
_beng
_erda
_cCaBNVSL
_dCaBNVSL
050 4 _aTK7871.95
_b.G555 2016
082 0 4 _a621.3815284
_223
100 1 _aGimenez, Salvador Pinillos,
_d1962-,
_eauthor.
245 1 0 _aLayout techniques for MOSFETS /
_cSalvador Pinillos Gimenez.
264 1 _aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) :
_bMorgan & Claypool,
_c2016.
300 _a1 PDF (xi, 69 pages) :
_billustrations.
336 _atext
_2rdacontent
337 _aelectronic
_2isbdmedia
338 _aonline resource
_2rdacarrier
490 1 _aSynthesis lectures on emerging engineering technologies,
_x2381-1439 ;
_v# 7
538 _aMode of access: World Wide Web.
538 _aSystem requirements: Adobe Acrobat Reader.
500 _aPart of: Synthesis digital library of engineering and computer science.
504 _aIncludes bibliographical references (pages 61-68).
505 0 _a1. Introduction -- 2. The origin of the innovative layout techniques for MOSFETs -- 2.1 Observing and combining different new effects in MOSFETs -- 3. Diamond MOSFET (hexagonal gate geometry) -- 4. Octo layout style (octagonal gate shape) for MOSFET -- 5. Ellipsoidal layout style for MOSFET -- 6. Fish layout style ("<" gate shape) for MOSFET -- 7. Annular circular gate layout style for MOSFET -- 8. Wave layout style ("S" gate shape) for MOSFET -- 9. Conclusions and comments -- References -- About the author.
506 1 _aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 _aCompendex
510 0 _aINSPEC
510 0 _aGoogle scholar
510 0 _aGoogle book search
520 3 _aThis book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on PN junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
530 _aAlso available in print.
588 _aTitle from PDF title page (viewed on April 14, 2016).
650 0 _aMetal oxide semiconductor field-effect transistors.
650 0 _aIntegrated circuit layout.
653 _alayout techniques
653 _aCircular Annular MOSFET
653 _apillar surrounding gate MOSFET
653 _aCynthia MOSFET
653 _aDiamond MOSFET
653 _aOcto MOSFET
653 _aEllipsoidal MOSFET
653 _aFish MOSFET
653 _aWave
653 _aMOSFET
653 _aLCE
653 _aPAMDLE
653 _aDEPAMBBRE
653 _aDLEFRE
653 _ahigh temperature
653 _aIonizing Radiation Effects
653 _aTID and SEE
776 0 8 _iPrint version:
_z9781627054881
830 0 _aSynthesis digital library of engineering and computer science.
830 0 _aSynthesis lectures on emerging engineering technologies ;
_v# 7.
_x2381-1439
856 4 2 _3Abstract with links to resource
_uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=7446015
999 _c562197
_d562197