000 | 07066nam a2200769 i 4500 | ||
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001 | 7416916 | ||
003 | IEEE | ||
005 | 20200413152920.0 | ||
006 | m eo d | ||
007 | cr cn |||m|||a | ||
008 | 160219s2016 cau foab 000 0 eng d | ||
020 |
_a9781627058551 _qebook |
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020 |
_z9781627058544 _qprint |
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024 | 7 |
_a10.2200/S00696ED1V01Y201601EET004 _2doi |
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035 | _a(CaBNVSL)swl00406217 | ||
035 | _a(OCoLC)940360713 | ||
040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
050 | 4 |
_aTK7874.75 _b.A835 2016 |
|
082 | 0 | 4 |
_a621.395 _223 |
100 | 1 |
_aAshraf, Nabil Shovon., _eauthor. |
|
245 | 1 | 0 |
_aNew prospects of integrating low substrate temperatures with scaling-sustained device architectural innovation / _cNabil Shovon Ashraf, Shawon Alam, and Mohaiminul Alam. |
264 | 1 |
_aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _c2016. |
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300 | _a1 PDF (viii, 72 pages) | ||
336 |
_atext _2rdacontent |
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337 |
_aelectronic _2isbdmedia |
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338 |
_aonline resource _2rdacarrier |
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490 | 1 |
_aSynthesis lectures on emerging engineering technologies, _x2381-1439 ; _v# 4 |
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538 | _aMode of access: World Wide Web. | ||
538 | _aSystem requirements: Adobe Acrobat Reader. | ||
500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
504 | _aIncludes bibliographical references (pages 63-69). | ||
505 | 0 | _a1. Review of research on scaled device architectures and importance of lower substrate temperature operation of n-MOSFETs -- 1.1 Introduction and scope of this e-book -- 1.2 Basic overview and operational salient features of n-channel MOSFET device transport -- 1.3 Review of challenges and bottlenecks experienced over sustained MOSFET device scaling -- 1.4 Device parameters critical for performance enhancement for generalized scaling and at the end of Moore's Law -- 1.5 Role of substrate temperature modeling and control -- | |
505 | 8 | _a2. Step-by-step computation of threshold voltage as a function of substrate temperatures -- 2.1 Essential modeling equations for computation of threshold voltage of N-channel MOSFET as a function of substrate/lattice temperature -- | |
505 | 8 | _a3.Simulation outcomes for profile of threshold voltage as a function of substrate temperature based on key device-centric parameters -- 3.1 Simulation outcomes of various n-MOSFET device parameters including threshold voltage as a function of temperature -- 3.2 Simulation outcome of intrinsic carrier concentration (ni ) as a function of substrate or lattice temperature -- 3.3 Simulation outcome of incomplete ionization of Dopants relevant for lower substrate temperature operation -- 3.4 Simulation outcome of Fermi energy level EF (eV) as a function of temperature -- 3.5 Temperature dependence of flat band voltage [phi]ms (V) -- 3.6 P-type substrate n-channel MOSFET bulk potential dependence on substrate/lattice temperature -- 3.7 Dependence of threshold voltage VT of n-channel MOSFET on substrate temperature for 1 micro channel length MOSFET -- 3.7.1 Modeling impact of incomplete ionization on threshold voltage at the freeze-out temperature region: a closer look -- 3.8 Threshold voltage dependence on substrate temperature for different substrate doping conditions for an n-channel MOSFET -- 3.9 Threshold voltage dependence on substrate temperature for different oxide thickness for an n-channel MOSFET -- 3.10 Threshold voltage dependence on substrate temperature for negative substrate bias for an n-channel MOSFET -- 3.11 Threshold voltage dependence on substrate temperature for positive substrate bias for an n-channel MOSFET -- | |
505 | 8 | _a4. Scaling projection of long channel threshold voltage variability with substrate temperatures to scaled node -- 4.1 Modeling and simulation results for a long channel MOSFET as channel length is scaled further -- | |
505 | 8 | _a5. Advantage of lower substrate temperature MOSFET operation to minimize short channel effects and enhance reliability -- 5.1 Low substrate temperature MOSFET modeling benefits in consideration of short channel effects -- | |
505 | 8 | _a6. A prospective outlook on implementation methodology of regulating substrate temperatures on silicon die -- 6.1 A short outlook on implementation of low substrate temperature MOSFET modeling and control -- | |
505 | 8 | _a7. Summary of research results -- 7.1 Summary of research outcomes -- | |
505 | 8 | _a8. Conclusion -- References -- Authors' biographies. | |
506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
510 | 0 | _aCompendex | |
510 | 0 | _aINSPEC | |
510 | 0 | _aGoogle scholar | |
510 | 0 | _aGoogle book search | |
520 | 3 | _aIn order to sustain Moore's Law-based device scaling, principal attention has focused on toward device architectural innovations for improved device performance as per ITRS projections for technology nodes up to 10 nm. Efficient integration of lower substrate temperatures (<300K) to these innovatively configured device structures can enable the industry professionals to keep up with Moore's Law-based scaling curve conforming with ITRS projection of device performance outcome values. In this prospective review E-book, the authors have systematically reviewed the research results based on scaled device architectures, identified key bottlenecks to sustained scaling-based performance, and through original device simulation outcomes of conventional long channel MOSFET extracted the variation profile of threshold voltage as a function of substrate temperature which will be instrumental in reducing subthreshold leakage current in the temperature range 100K-300K. An exploitation methodology to regulate the die temperature to enable the efficient performance of a high-density VLSI circuit is also documented in order to make the lower substrate temperature operation of VLSI circuits and systems on chip process compatible. | |
530 | _aAlso available in print. | ||
588 | _aTitle from PDF title page (viewed on February 19, 2016). | ||
650 | 0 |
_aIntegrated circuits _xVery large scale integration. |
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650 | 0 | _aComputer engineering. | |
650 | 0 | _aLow temperature engineering. | |
653 | _athreshold voltage | ||
653 | _asubstrate temperature | ||
653 | _aFermi potential | ||
653 | _aintrinsic carrier concentration | ||
653 | _abulk potential | ||
653 | _adepletion charge | ||
653 | _ametal-to-semiconductor work function difference | ||
653 | _aflat-band voltage | ||
653 | _asubthreshold leakage current | ||
653 | _athin-film microcoolers | ||
700 | 1 |
_aAlam, Shawon., _eauthor. |
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700 | 1 |
_aAlam, Mohaiminul., _eauthor. |
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776 | 0 | 8 |
_iPrint version: _z9781627058544 |
830 | 0 | _aSynthesis digital library of engineering and computer science. | |
830 | 0 |
_aSynthesis lectures on emerging engineering technologies ; _v# 4. _x2381-1439 |
|
856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=7416916 |
999 |
_c562188 _d562188 |