| 000 | 05142nam a2200709 i 4500 | ||
|---|---|---|---|
| 001 | 7347037 | ||
| 003 | IEEE | ||
| 005 | 20200413152919.0 | ||
| 006 | m eo d | ||
| 007 | cr cn |||m|||a | ||
| 008 | 151124s2016 caua foab 000 0 eng d | ||
| 020 |
_a9781627058322 _qebook |
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| 020 |
_z9781627058315 _qprint |
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| 024 | 7 |
_a10.2200/S00677ED1V01Y201511CAC034 _2doi |
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| 035 | _a(CaBNVSL)swl00405829 | ||
| 035 | _a(OCoLC)930370858 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
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| 050 | 4 |
_aTK7895.M5 _bS427 2016 |
|
| 082 | 0 | 4 |
_a621.3916 _223 |
| 100 | 1 |
_aShao, Yakun Sophia., _eauthor. |
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| 245 | 1 | 0 |
_aResearch infrastructures for hardware accelerators / _cYakun Sophia Shao and David Brooks. |
| 264 | 1 |
_aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _c2016. |
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| 300 |
_a1 PDF (xiii, 85 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 490 | 1 |
_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 34 |
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| 538 | _aMode of access: World Wide Web. | ||
| 538 | _aSystem requirements: Adobe Acrobat Reader. | ||
| 500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
| 504 | _aIncludes bibliographical references (pages 73-83). | ||
| 505 | 0 | _a1. Why accelerators, now? -- 1.1 What is an accelerator? -- 1.2 A tale of two scalings -- 1.2.1 Moore scaling -- 1.2.2 Dennard scaling -- 1.3 The combination of Moore and Dennard scaling -- 1.3.1 Moore + Dennard, where we were -- 1.3.2 Moore scaling only, where we are -- 1.3.3 Dennard only, where we are unlikely to be -- 1.3.4 A future without scaling: "The winter of despair" -- 1.4 To live without scaling: "A spring of hope" -- 1.4.1 Why not architectural scaling? -- 1.4.2 Specialization makes a difference -- 1.4.3 A call for tools in the era of accelerators -- | |
| 505 | 8 | _a2. A taxonomy of accelerators -- 2.1 Not all apples are alike -- 2.2 Accelerator taxonomy -- 2.2.1 Accelerators that are part of the pipeline -- 2.2.2 Accelerators that are attached to cache -- 2.2.3 Accelerators that are attached to the memory bus -- 2.2.4 Accelerators that are attached to the I/O bus -- | |
| 505 | 8 | _a3. Accelerator design flow 101 -- 3.1 Standard RTL design flow -- 3.2 High-level synthesis -- 3.2.1 Bluespec SystemVerilog -- 3.2.2 Genesis2 -- 3.2.3 Xilinx Vivado -- 3.2.4 Delite -- 3.2.5 Lime -- 3.2.6 ChiseL -- 3.2.7 Spiral -- 3.2.8 PyMTL -- | |
| 505 | 8 | _a4. Accelerator modeling -- 4.1 Limitations of the RTL-based design flow -- 4.2 Pre-RTL modeling, Aladdin -- 4.2.1 Optimization phase -- 4.2.2 Realization phase -- 4.2.3 Integration with memory system -- 4.2.4 Limitations -- 4.2.5 Aladdin validation -- 4.2.6 Algorithm-to-solution time -- 4.2.7 Case study: Gemm design space -- | |
| 505 | 8 | _a5. Workload characterization for accelerators -- 5.1 ISA-independent workload characterization, WIICA -- 5.1.1 Why ISA-independent? -- 5.1.2 Methodology and background -- 5.1.3 Compute -- 5.1.4 Memory -- 5.1.5 Control -- 5.1.6 Putting it all together -- | |
| 505 | 8 | _a6. Accelerator benchmarks -- | |
| 505 | 8 | _a7. Future directions -- Bibliography -- Authors' biographies. | |
| 506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
| 510 | 0 | _aCompendex | |
| 510 | 0 | _aINSPEC | |
| 510 | 0 | _aGoogle scholar | |
| 510 | 0 | _aGoogle book search | |
| 520 | 3 | _aHardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas. | |
| 530 | _aAlso available in print. | ||
| 588 | _aTitle from PDF title page (viewed on November 24, 2015). | ||
| 650 | 0 |
_aMicroprocessors _xDesign and construction. |
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| 650 | 0 | _aHigh performance computing. | |
| 653 | _aaccelerators | ||
| 653 | _aspecialized architecture | ||
| 653 | _aSoC | ||
| 653 | _ahigh-level synthesis, | ||
| 653 | _asimulators | ||
| 653 | _adesign space exploration | ||
| 653 | _aworkload characterization | ||
| 653 | _abenchmarks | ||
| 700 | 1 |
_aBrooks, David., _eauthor. |
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| 776 | 0 | 8 |
_iPrint version: _z9781627058315 |
| 830 | 0 | _aSynthesis digital library of engineering and computer science. | |
| 830 | 0 |
_aSynthesis lectures in computer architecture ; _v# 34. _x1935-3243 |
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| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=7347037 |
| 999 |
_c562172 _d562172 |
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