| 000 | 05472nam a2200661 i 4500 | ||
|---|---|---|---|
| 001 | 7036193 | ||
| 003 | IEEE | ||
| 005 | 20200413152916.0 | ||
| 006 | m eo d | ||
| 007 | cr cn |||m|||a | ||
| 008 | 150117s2015 caua foab 000 0 eng d | ||
| 020 |
_a9781627056465 _qebook |
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| 020 |
_z9781627056458 _qprint |
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| 024 | 7 |
_a10.2200/S00611ED1V01Y201411CAC030 _2doi |
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| 035 | _a(CaBNVSL)swl00404601 | ||
| 035 | _a(OCoLC)900340877 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aQA76.9.A73 _bS526 2015 |
|
| 082 | 0 | 4 |
_a004.22 _223 |
| 100 | 1 |
_aSjälander, Magnus, _d1977-, _eauthor. |
|
| 245 | 1 | 0 |
_aPower-efficient computer architectures : _brecent advances / _cMagnus Själander, Margaret Martonosi, Stefanos Kaxiras. |
| 264 | 1 |
_aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _c2015. |
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| 300 |
_a1 PDF (xi, 84 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 490 | 1 |
_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 30 |
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| 538 | _aMode of access: World Wide Web. | ||
| 538 | _aSystem requirements: Adobe Acrobat Reader. | ||
| 500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
| 504 | _aIncludes bibliographical references (pages 61-81). | ||
| 505 | 0 | _a1. Introduction -- 1.1 From the beginning -- 1.2 The end of Dennard scaling and the switch to multicores -- 1.3 Dark silicon, the utilization wall, and the rise of the heterogeneous parallelism -- 1.4 Other issues and future directions -- 1.5 About the book -- 1.5.1 Differences from the prior synthesis lecture [103] -- 1.5.2 Target audience -- | |
| 505 | 8 | _a2. Voltage and frequency management -- 2.1 Technology background and trends -- 2.1.1 Relation of V and f -- 2.1.2 Technology solutions -- 2.1.3 DVFS latency -- 2.1.4 DVFS granularity -- 2.2 Models of frequency vs. performance and power -- 2.2.1 Analytical models -- 2.2.2 Correlation-based power models -- 2.2.3 A combined power and performance model -- 2.3 OS-managed DVFS techniques -- 2.3.1 Discovering and exploiting deadlines -- 2.3.2 Linux DVFS governors -- 2.4 Parallelism and criticality -- 2.4.1 Thread- and task-level criticality: static scheduling -- 2.4.2 Thread- and task-level criticality: dynamic scheduling -- 2.4.3 Criticality -- 2.5 Chapter summary -- | |
| 505 | 8 | _a3. Heterogeneity and specialization -- 3.1 Dark silicon -- 3.1.1 Dark silicon analysis and models -- 3.1.2 Designing for dark silicon: brief examples -- 3.1.3 The sentiments against dark silicon -- 3.2 Heterogeneity in on-chip CPUs -- 3.2.1 Current industry approaches -- 3.2.2 Research and future trends -- 3.3 Single-ISA configurable heterogeneity -- 3.4 Mixing GPUs and CPUs -- 3.4.1 CPU-GPU pairs: the power-performance rationale -- 3.4.2 Industry examples -- 3.4.3 Selected research examples -- 3.5 Accelerators -- 3.5.1 Background -- 3.5.2 Selected research -- 3.5.3 Industry examples -- 3.6 Reliability vs. energy tradeoffs -- 3.7 Chapter summary -- | |
| 505 | 8 | _a4. Communication and memory systems -- 4.1 The energy cost of data motion: a holistic view -- 4.2 Power awareness in on-chip interconnect: techniques and trends -- 4.2.1 Background and industry state -- 4.2.2 Power efficiency of interconnect links -- 4.2.3 Exploiting emerging technologies to improve power efficiency -- 4.3 Power awareness in data storage: caches and scratchpads -- 4.3.1 Cache hierarchies and power efficiency -- 4.3.2 Cache associativity and its implication on power -- 4.3.3 Cache resizing and static power -- 4.3.4 Cache coherence -- 4.3.5 The power implications of scratchpad memories -- 4.4 Chapter summary -- | |
| 505 | 8 | _a5. Conclusions -- 5.1 Future trends: technology challenges and drivers -- 5.2 Future trends: emerging applications and domains -- 5.3 Final summary -- Bibliography -- Authors' biographies. | |
| 506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
| 510 | 0 | _aCompendex | |
| 510 | 0 | _aINSPEC | |
| 510 | 0 | _aGoogle scholar | |
| 510 | 0 | _aGoogle book search | |
| 520 | 3 | _aAs Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture. | |
| 530 | _aAlso available in print. | ||
| 588 | _aTitle from PDF title page (viewed on January 17, 2015). | ||
| 650 | 0 | _aComputer architecture. | |
| 650 | 0 |
_aElectronic digital computers _xPower supply. |
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| 650 | 0 |
_aElectric power _xConservation. |
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| 653 | _apower | ||
| 653 | _aarchitecture | ||
| 653 | _aparallelism | ||
| 653 | _aheterogeneity | ||
| 700 | 1 |
_aMartonosi, Margaret., _eauthor. |
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| 700 | 1 |
_aKaxiras, Stefanos., _eauthor. |
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| 776 | 0 | 8 |
_iPrint version: _z9781627056458 |
| 830 | 0 | _aSynthesis digital library of engineering and computer science. | |
| 830 | 0 |
_aSynthesis lectures in computer architecture ; _v# 30. _x1935-3243 |
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| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=7036193 |
| 999 |
_c562111 _d562111 |
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