000 06134nam a2200721 i 4500
001 6894333
003 IEEE
005 20200413152915.0
006 m eo d
007 cr cn |||m|||a
008 140918s2014 caua foab 000 0 eng d
020 _a9781627052146
_qebook
020 _z9781627052139
_qprint
024 7 _a10.2200/S00586ED1V01Y201407CAC029
_2doi
035 _a(CaBNVSL)swl00403921
035 _a(OCoLC)890973752
040 _aCaBNVSL
_beng
_erda
_cCaBNVSL
_dCaBNVSL
050 4 _aTK7895.G36
_bA533 2014
082 0 4 _a621.395
_223
090 _a
_bMoCl
_e201407CAC029
100 1 _aAngepat, Hari.,
_eauthor.
245 1 0 _aFPGA-accelerated simulation of computer systems /
_cHari Angepat, Derek Chiou, Eric S. Chung, James C. Hoe.
264 1 _aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) :
_bMorgan & Claypool,
_c2014.
300 _a1 PDF (xv, 64 pages) :
_billustrations.
336 _atext
_2rdacontent
337 _aelectronic
_2isbdmedia
338 _aonline resource
_2rdacarrier
490 1 _aSynthesis lectures on computer architecture,
_x1935-3243 ;
_v# 29
538 _aMode of access: World Wide Web.
538 _aSystem requirements: Adobe Acrobat Reader.
500 _aPart of: Synthesis digital library of engineering and computer science.
504 _aIncludes bibliographical references (pages 57-61).
505 0 _a1. Introduction -- 1.1 Overview -- 1.2 Host vs. target terminology -- 1.3 Why are fast, accurate simulators of computer targets needed? -- 1.4 Harnessing FPGAs for simulation not prototyping -- 1.5 The rest of the book --
505 8 _a2. Simulator background -- 2.1 Uses of computer simulation -- 2.2 Desired simulator characteristics -- 2.3 Performance simulation accuracy -- 2.4 Simulator design tradeoff -- 2.5 Simulator partitioning for parallelization -- 2.5.1 Spatial partitioning -- 2.5.2 Temporal partitioning -- 2.5.3 Functional/timing partitioning -- 2.5.4 Hybrid partitioning -- 2.6 Functional/timing simulation architectures -- 2.6.1 Monolithic simulators -- 2.6.2 Timing-directed simulators -- 2.6.3 Functional-first simulators -- 2.6.4 Timing-first simulators -- 2.6.5 Speculative functional-first -- 2.7 Simulation events and synchronization -- 2.7.1 Centralized synchronization -- 2.7.2 Decentralized event synchronization --
505 8 _a3. Accelerating computer system simulators with FPGAs -- 3.1 Exploiting target partitioning on FPGAs -- 3.2 Accelerating traditional simulator architectures with FPGAs -- 3.2.1 Accelerating monolithic simulators with FPGAs -- 3.2.2 Accelerating timing-directed simulators with FPGAs -- 3.2.3 Accelerating functional-first simulators with FPGAs -- 3.2.4 Accelerating timing-first simulators with FPGAs -- 3.2.5 Accelerating speculative functional-first with FPGAs -- 3.2.6 Accelerating combined simulator architectures with FPGAs -- 3.3 Managing time through simulation event sychronization in an FPGA-accelerated simulator -- 3.3.1 Centralized barrier synchronization in an FPGA-accelerated simulator -- 3.3.2 Decentralized barrier synchronization in an FPGA-accelerated simulator -- 3.4 FPGA simulator programmability -- 3.5 Case study: FPGA-accelerated simulation technologies (FAST) --
505 8 _a4. Simulation virtualization -- 4.1 Full-system and multiprocessor simulation -- 4.2 Hierarchical simulation with transplanting -- 4.2.1 Hierarchical simulation -- 4.2.2 Transplanting -- 4.2.3 Hierarchical transplanting -- 4.3 Virtualized simulation of multiprocessors -- 4.3.1 Time-multiplexed virtualization -- 4.3.2 Virtualizing memory capacity -- 4.4 Case study: the Protoflex simulator -- 4.4.1 ProtoFlex design overview -- 4.4.2 BlueSPARC pipeline -- 4.4.3 Performance evaluation -- 4.4.4 Hierarchical simulation and virtualization in a performance simulator --
505 8 _a5. Categorizing FPGA-based simulators -- 5.1 Fame classifications -- 5.2 Open-sourced FPGA-based simulators -- 5.2.1 ProtoFlex -- 5.2.2 HAsim -- 5.2.3 RAMP Gold --
505 8 _a6. Conclusion -- A. Field programmable gate arrays -- Programmable logic elements -- Embedded SRAM blocks -- Hard "macros" -- Bibliography -- Authors' biographies.
506 1 _aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 _aCompendex
510 0 _aINSPEC
510 0 _aGoogle scholar
510 0 _aGoogle book search
520 3 _aTo date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed for FPGA accelerated simulation, survey the state-of the- art in FPGA-accelerated simulation, and describe in detail selected instances of the described techniques.
530 _aAlso available in print.
588 _aTitle from PDF title page (viewed on September 18, 2014).
650 0 _aField programmable gate arrays.
650 0 _aComputer systems
_xComputer simulation.
650 0 _aComputer simulation.
653 _asimulation
653 _acycle-accurate
653 _afunctional
653 _atiming
653 _aFPGA accelerated
700 1 _aChiou, Derek.,
_eauthor.
700 1 _aChung, Eric S.,
_eauthor.
700 1 _aHoe, James C.,
_eauthor.
776 0 8 _iPrint version:
_z9781627052139
830 0 _aSynthesis digital library of engineering and computer science.
830 0 _aSynthesis lectures in computer architecture ;
_v# 29.
_x1935-3243
856 4 0 _3Abstract with links to full text
_uhttp://dx.doi.org/10.2200/S00586ED1V01Y201407CAC029
856 4 2 _3Abstract with links to resource
_uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6894333
999 _c562085
_d562085