| 000 | 05455nam a2200733 i 4500 | ||
|---|---|---|---|
| 001 | 6812848 | ||
| 003 | IEEE | ||
| 005 | 20200413152912.0 | ||
| 006 | m eo d | ||
| 007 | cr cn |||m|||a | ||
| 008 | 131113s2014 caua foab 000 0 eng d | ||
| 020 |
_a9781627052122 _qebook |
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| 020 |
_z9781627052115 _qpaperback |
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| 024 | 7 |
_a10.2200/S00537ED1V01Y201309CAC027 _2doi |
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| 035 | _a(CaBNVSL)swl00402945 | ||
| 035 | _a(OCoLC)862937555 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
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| 050 | 4 |
_aTK7874.53 _b.N576 2014 |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 090 |
_a _bMoCl _e201309CAC027 |
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| 100 | 1 |
_aNitta, Christopher J., _eauthor. |
|
| 245 | 1 | 0 |
_aOn-chip photonic interconnects : _ba computer architect's perspective / _cChristopher J. Nitta, Matthew K. Farrens, and Venkatesh Akella. |
| 264 | 1 |
_aSan Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _c2014. |
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| 300 |
_a1 PDF (xix, 91 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 490 | 1 |
_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 27 |
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| 538 | _aMode of access: World Wide Web. | ||
| 538 | _aSystem requirements: Adobe Acrobat Reader. | ||
| 500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
| 500 | _aSeries from website. | ||
| 504 | _aIncludes bibliographical references (pages 77-90). | ||
| 505 | 0 | _aList of figures -- List of tables -- List of acronyms -- Acknowledgments -- 1. Introduction -- 1.1 Organization of the lecture -- | |
| 505 | 8 | _a2. Photonic interconnect basics -- 2.1 Transmitter -- 2.1.1 Lasers -- 2.1.2 Microring resonators -- 2.1.3 Microrings as modulators -- 2.2 Transmission medium -- 2.2.1 Waveguide details -- 2.2.2 Vias -- 2.3 Receiver -- 2.3.1 Photodetector details -- | |
| 505 | 8 | _a3. Link construction -- 3.1 Photonic link design -- 3.1.1 Transmitter -- 3.1.2 Transmission medium -- 3.1.3 Receiver -- 3.1.4 Design decisions -- 3.1.5 Photonic power requirements -- 3.1.6 Electronic power requirements -- 3.1.7 Layout/implementation issues -- 3.1.8 Wide and slow or narrow and fast? -- 3.1.9 Total power -- | |
| 505 | 8 | _a4. On-chip photonic networks -- 4.1 Photonic network design challenges -- 4.1.1 Buffering -- 4.1.2 Topology -- 4.1.3 Arbitration and flow control -- 4.1.4 Electrical/optical codesign -- 4.1.5 Latency -- 4.2 Case studies of on-chip photonic networks -- 4.2.1 Corona -- 4.2.2 Phastlane -- 4.2.3 Firefly -- 4.2.4 Flexishare -- 4.2.5 DCAF -- 4.2.6 Hybrid photonic NoC -- | |
| 505 | 8 | _a5. Challenges -- 5.1 Process variations -- 5.2 Thermal issues -- 5.3 Trimming -- 5.4 Resilient on-chip photonic networks -- 5.4.1 Photonic link fault models -- 5.4.2 Link component structure-dependent errors -- 5.4.3 Unidirectional bit errors -- 5.4.4 Mean time between failures -- | |
| 505 | 8 | _a6. Other developments -- 6.1 On-chip network developments -- 6.1.1 Monolithic CMOS integration -- 6.1.2 Lasers -- 6.1.3 Plasmonics -- 6.2 System-level developments -- 6.2.1 Off-chip I/O -- 6.2.2 Memory system -- 6.2.3 Large-scale routers -- | |
| 505 | 8 | _a7. Summary & conclusion -- 7.1 Observations and things to remember -- Bibliography -- Authors' biographies. | |
| 506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
| 510 | 0 | _aCompendex | |
| 510 | 0 | _aINSPEC | |
| 510 | 0 | _aGoogle scholar | |
| 510 | 0 | _aGoogle book search | |
| 520 | 3 | _aAs the number of cores on a chip continues to climb, architects will need to address both band-width and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks. | |
| 530 | _aAlso available in print. | ||
| 588 | _aTitle from PDF title page (viewed on November 13, 2013). | ||
| 650 | 0 | _aInterconnects (Integrated circuit technology) | |
| 650 | 0 | _aNanophotonics. | |
| 653 | _ananophotonics | ||
| 653 | _aon-chip network | ||
| 653 | _ainterconnect | ||
| 653 | _amicroring | ||
| 653 | _aoptical interconnects | ||
| 653 | _anetwork topologies | ||
| 700 | 1 |
_aFarrens, Matthew K., _eauthor. |
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| 700 | 1 |
_aAkella, Venkatesh, _d1982-, _eauthor. |
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| 776 | 0 | 8 |
_iPrint version: _z9781627052115 |
| 830 | 0 | _aSynthesis digital library of engineering and computer science. | |
| 830 | 0 |
_aSynthesis lectures in computer architecture ; _v# 27. _x1935-3243 |
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| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6812848 |
| 856 | 4 | 0 |
_3Abstract with links to full text _uhttp://dx.doi.org/10.2200/S00537ED1V01Y201309CAC027 |
| 999 |
_c562034 _d562034 |
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