| 000 | 05842nam a2200637 i 4500 | ||
|---|---|---|---|
| 001 | 6812580 | ||
| 003 | IEEE | ||
| 005 | 20200413152909.0 | ||
| 006 | m eo d | ||
| 007 | cr cn |||m|||a | ||
| 008 | 130217s2013 caua foab 000 0 eng d | ||
| 020 | _a9781608458561 (electronic bk.) | ||
| 020 | _z9781608458554 (pbk.) | ||
| 024 | 7 |
_a10.2200/S00458ED1V01Y201212CAC021 _2doi |
|
| 035 | _a(CaBNVSL)swl00402158 | ||
| 035 | _a(OCoLC)827936289 | ||
| 040 |
_aCaBNVSL _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aQA76.9.A73 _bN455 2013 |
|
| 082 | 0 | 4 |
_a004.22 _223 |
| 100 | 1 | _aNemirovsky, Mario. | |
| 245 | 1 | 0 |
_aMultithreading architecture _h[electronic resource] / _cMario Nemirovsky, Dean M. Tullsen. |
| 260 |
_aSan Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _cc2013. |
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| 300 |
_a1 electronic text (xiv, 95 p.) : _bill., digital file. |
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| 490 | 1 |
_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 21 |
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| 538 | _aMode of access: World Wide Web. | ||
| 538 | _aSystem requirements: Adobe Acrobat Reader. | ||
| 500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
| 500 | _aSeries from website. | ||
| 504 | _aIncludes bibliographical references (p. 83-94). | ||
| 505 | 0 | _aPreface -- 1. Introduction -- | |
| 505 | 8 | _a2. Multithreaded execution models -- 2.1 Chip multiprocessors -- 2.2 Conjoined core architectures -- 2.3 Coarse-grain multithreading -- 2.4 Fine-grain multithreading -- 2.5 Simultaneous multithreading -- 2.6 Hybrid models -- 2.7 GPUs and warp scheduling -- 2.8 Summary -- | |
| 505 | 8 | _a3. Coarse-grain multithreading -- 3.1 Historical context -- 3.2 A reference implementation of CGMT -- 3.2.1 Changes to IF -- 3.2.2 Changes to RD -- 3.2.3 Changes to ALU -- 3.2.4 Changes to MEM -- 3.2.5 Changes to WB -- 3.2.6 Swapping contexts -- 3.2.7 Superscalar considerations -- 3.3 Coarse-grain multithreading for modern architectures -- | |
| 505 | 8 | _a4. Fine-grain multithreading -- 4.1 Historical context -- 4.2 A reference implementation of FGMT -- 4.2.1 Changes to IF -- 4.2.2 Changes to RD -- 4.2.3 Changes to ALU -- 4.2.4 Changes to MEM -- 4.2.5 Changes to WB -- 4.2.6 Superscalar considerations -- 4.3 Fine-grain multithreading for modern architectures -- | |
| 505 | 8 | _a5. Simultaneous multithreading -- 5.1 Historical context -- 5.2 A reference implementation of SMT -- 5.2.1 Changes to fetch -- 5.2.2 Changes to DEC/MAP -- 5.2.3 Changes to Issue/RF -- 5.2.4 Other pipeline stages -- 5.3 Superscalar vs. VLIW; in-order vs. out-of-order -- 5.4 Simultaneous multithreading for modern architectures -- | |
| 505 | 8 | _a6. Managing contention -- 6.1 Managing cache and memory contention -- 6.2 Branch predictor contention -- 6.3 Managing contention through the fetch unit -- 6.4 Managing register files -- 6.5 Operating system thread scheduling -- 6.6 Compiling for multithreaded processors -- 6.7 Multithreaded processor synchronization -- 6.8 Security on multithreaded systems -- | |
| 505 | 8 | _a7. New opportunities for multithreaded processors -- 7.1 Helper threads and non-traditional parallelism -- 7.2 Fault tolerance -- 7.3 Speculative multithreading on multithreaded processors -- 7.4 Energy and power -- | |
| 505 | 8 | _a8. Experimentation and metrics -- | |
| 505 | 8 | _a9. Implementations of multithreaded processors -- 9.1 Early machines, DYSEAC and the Lincoln TX-2 -- 9.2 CDC 6600 -- 9.3 Denelcor HEP -- 9.4 Horizon -- 9.5 Delco TIO -- 9.6 Tera MTA -- 9.7 MIT Sparcle -- 9.8 DEC/Compaq Alpha 21464 -- 9.9 Clearwater Networks CNP810SP -- 9.10 ConSentry Networks LSP-1 -- 9.11 Pentium 4 -- 9.12 Sun Ultrasparc (Niagara) T1 and T2 -- 9.13 Sun MAJC and ROCK -- 9.14 IBM Power -- 9.15 AMD Bulldozer -- 9.16 Intel Nehalem -- 9.17 Summary -- | |
| 505 | 8 | _aBibliography -- Authors' biographies. | |
| 506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
| 510 | 0 | _aCompendex | |
| 510 | 0 | _aINSPEC | |
| 510 | 0 | _aGoogle scholar | |
| 510 | 0 | _aGoogle book search | |
| 520 | 3 | _aMultithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not cause execution resources to be idle. This enables the computer architect to maximize performance within area constraints, power constraints, or energy constraints. However, the architectural options for the processor designer or architect looking to implement multithreading are quite extensive and varied, as evidenced not only by the research literature but also by the variety of commercial implementations. This book introduces the basic concepts of multithreading, describes the a number of models of multithreading, and then develops the three classic models (coarse-grain, fine-grain, and simultaneous multithreading) in greater detail. It describes a wide variety of architectural and software design tradeoffs, as well as opportunities specific to multithreading architectures. Finally, it details a number of important commercial and academic hardware implementations of multithreading. | |
| 530 | _aAlso available in print. | ||
| 588 | _aTitle from PDF t.p. (viewed on February 17, 2013). | ||
| 650 | 0 | _aSimultaneous multithreading processors. | |
| 650 | 0 | _aComputer architecture. | |
| 653 | _amultithreading | ||
| 700 | 1 | _aTullsen, Dean M. | |
| 776 | 0 | 8 |
_iPrint version: _z9781608458554 |
| 830 | 0 | _aSynthesis digital library of engineering and computer science. | |
| 830 | 0 |
_aSynthesis lectures in computer architecture ; _v# 21. _x1935-3243 |
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| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6812580 |
| 999 |
_c561970 _d561970 |
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