| 000 | 06772nam a2200673 i 4500 | ||
|---|---|---|---|
| 001 | 6813358 | ||
| 003 | IEEE | ||
| 005 | 20200413152904.0 | ||
| 006 | m eo d | ||
| 007 | cr cn |||m|||a | ||
| 008 | 111217s2012 caua foab 000 0 eng d | ||
| 020 | _a9781608456666 (electronic bk.) | ||
| 020 | _z9781608456659 (pbk.) | ||
| 024 | 7 |
_a10.2200/S00381ED1V01Y201109CAC018 _2doi |
|
| 035 | _a(CaBNVSL)swl00400318 | ||
| 035 | _a(OCoLC)767747932 | ||
| 040 |
_aCaBNVSL _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK7895.M4 _bQ746 2012 |
|
| 082 | 0 | 4 |
_a004.5 _222 |
| 100 | 1 |
_aQureshi, Moinuddin Khalil Ahmed, _d1978- |
|
| 245 | 1 | 0 |
_aPhase change memory _h[electronic resource] : _bfrom devices to systems / _cMoinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran. |
| 260 |
_aSan Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool, _cc2012. |
||
| 300 |
_a1 electronic text (xiii, 120 p.) : _bill., digital file. |
||
| 490 | 1 |
_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 18 |
|
| 538 | _aMode of access: World Wide Web. | ||
| 538 | _aSystem requirements: Adobe Acrobat Reader. | ||
| 500 | _aPart of: Synthesis digital library of engineering and computer science. | ||
| 500 | _aSeries from website. | ||
| 504 | _aIncludes bibliographical references (p. 95-118). | ||
| 505 | 0 | _a1. Next generation memory technologies -- 1.1 Introduction -- 1.2 Next generation memory technologies, a desiderata -- 1.3 Overview of flash memory and other leading contenders -- 1.3.1 Flash memory -- 1.3.2 Ferro-electric RAM -- 1.3.3 Magnetic & spin-torque transfer RAM -- 1.3.4 Resistive RAM -- 1.3.5 Emerging memory candidates at a glance -- 1.4 Phase change memory -- 1.4.1 PCM materials/device physics -- 1.4.2 Physics of PCM programming and scaling theory -- 1.4.3 Memory cell and array design -- 1.4.4 MLC programming in PCM -- 1.4.5 Reliability -- 1.4.6 PCM technology maturity -- 1.4.7 Concluding remarks -- | |
| 505 | 8 | _a2. Architecting PCM for main memories -- 2.1 Introduction -- 2.2 PCM benefits and challenges -- 2.3 PCM tailored array organization -- 2.4 Fine-grained write filtering -- 2.5 Hybrid memory: combining DRAM and PCM -- 2.5.1 Optimizations for hybrid memory -- 2.5.2 Performance of hybrid memory -- 2.6 Concluding -- | |
| 505 | 8 | _a3. Tolerating slow writes in PCM -- 3.1 Introduction -- 3.2 Problem: contention from slow writes -- 3.3 Write cancellation for PCM -- 3.4 Threshold-based write cancellation -- 3.5 Adaptive write cancellation -- 3.6 Overheads: extraneous writes -- 3.7 Pausing in iterative-write devices -- 3.8 Write pausing -- 3.9 Combining write pausing and cancellation -- 3.10 Impact of write queue size -- 3.11 Concluding remarks -- | |
| 505 | 8 | _a4. Wear leveling for durability -- 4.1 Introduction -- 4.2 Figure of merit for effective wear leveling -- 4.3 Start-gap wear leveling -- 4.3.1 Design -- 4.3.2 Mapping of addresses -- 4.3.3 Overheads -- 4.3.4 Results for start-gap -- 4.3.5 A shortcoming of start-gap -- 4.4 Randomized start-gap -- 4.4.1 Feistel network based randomization -- 4.4.2 Random invertible binary matrix -- 4.4.3 Results of randomized start-gap -- 4.5 Concluding remarks -- | |
| 505 | 8 | _a5. Wear leveling under adversarial settings -- 5.1 Introduction -- 5.2 A simple attack kernel -- 5.3 Summary of secure wear leveling algorithms -- 5.4 Formulating secure wear leveling as buckets-and-balls problem -- 5.5 Write overhead of secure wear leveling -- 5.6 Adaptive wear leveling -- 5.6.1 Architecture -- 5.6.2 Attack density -- 5.6.3 Attack density for typical applications -- 5.7 Online attack detection -- 5.8 Anatomy of an attack -- 5.9 Practical attack detection -- 5.10 Implementing adaptive wear leveling -- 5.10.1 Adaptive start gap -- 5.10.2 Adaptive security refresh (SR-1) -- 5.10.3 Adaptive security refresh (SR-M) -- 5.11 Concluding remarks -- | |
| 505 | 8 | _a6. Error resilience in phase change memories -- 6.1 Introduction -- 6.2 Fault model assumptions -- 6.3 Dynamically replicated memory -- 6.3.1 Structure -- 6.3.2 Page compatibility -- 6.3.3 Error detection -- 6.3.4 Low overhead approximate pairing -- 6.4 Error correcting pointers -- 6.5 Alternate data retry and safer -- 6.6 Fine-grained embedded redirection -- 6.7 Concluding remarks -- | |
| 505 | 8 | _a7. Storage and system design with emerging non-volatile memories -- 7.1 Introduction and chapter overview -- 7.2 Storage-class memory, a system level abstraction for phase change memory -- 7.3 Storage system design -- 7.3.1 Overview of solid-state disks -- 7.3.2 The flash translation layer (FTL) -- 7.4 FTL and SSD design optimizations with storage-class memory -- 7.4.1 Addressing the small-write problem of flash SSDs -- 7.4.2 New SSD interfaces -- 7.4.3 Case study: the onyx PCM-based SSD -- 7.4.4 Discussion -- 7.5 Implications of memory system non-volatility on system design -- 7.5.1 File system design -- 7.5.2 The software interface to SCM -- 7.5.3 Non-volatility as a design knob -- 7.5.4 Discussion -- | |
| 505 | 8 | _aBibliography -- Authors' biographies. | |
| 506 | 1 | _aAbstract freely available; full-text restricted to subscribers or individual document purchasers. | |
| 510 | 0 | _aCompendex | |
| 510 | 0 | _aINSPEC | |
| 510 | 0 | _aGoogle scholar | |
| 510 | 0 | _aGoogle book search | |
| 520 | 3 | _aAs conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveying the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. | |
| 530 | _aAlso available in print. | ||
| 588 | _aTitle from PDF t.p. (viewed on December 17, 2011). | ||
| 650 | 0 | _aComputer storage devices. | |
| 650 | 0 | _aRandom access memory. | |
| 653 | _aphase change memory | ||
| 653 | _anon-volatile memory | ||
| 653 | _astorage | ||
| 653 | _adisks | ||
| 653 | _asystems | ||
| 700 | 1 | _aGurumurthi, Sudhanva. | |
| 700 | 1 | _aRajendran, Bipin. | |
| 776 | 0 | 8 |
_iPrint version: _z9781608456659 |
| 830 | 0 | _aSynthesis digital library of engineering and computer science. | |
| 830 | 0 |
_aSynthesis lectures in computer architecture ; _v# 18. _x1935-3243 |
|
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6813358 |
| 999 |
_c561888 _d561888 |
||