000			05965nam a2200565 i 4500
001			6812992
003			IEEE
005			20200413152855.0
006			m eo d
007			cr cn |||m|||a
008			090809s2009 caua foab 000 0 eng d
020			_a9781598295856 (electronic bk.)
020			_z9781598295849 (pbk.)
024	7		_a10.2200/S00209ED1V01Y200907CAC008 _2doi
035			_a(CaBNVSL)gtp00535456
035			_a(OCoLC)428595223
040			_aCaBNVSL _cCaBNVSL _dCaBNVSL
050		4	_aTK5105.546 _b.E575 2009
082	0	4	_a004.1 _222
100	1		_aEnright Jerger, Natalie D.
245	1	0	_aOn-chip networks _h[electronic resource] / _cNatalie Enright Jerger, Li-Shiuan Peh.
260			_aSan Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool Publishers, _cc2009.
300			_a1 electronic text (xii, 127 p. : ill.) : _bdigital file.
490	1		_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 8
538			_aMode of access: World Wide Web.
538			_aSystem requirements: Adobe Acrobat reader.
500			_aPart of: Synthesis digital library of engineering and computer science.
500			_aSeries from website.
504			_aIncludes bibliographical references (p. 105-125).
505	0		_aIntroduction -- The advent of the multi-core era -- Communication demands of multi-core architectures -- On-chip vs. off-chip networks -- Network basics: a quick primer -- Evolution to on-chip networks -- On-chip network building blocks -- Performance and cost -- Commercial on-chip network chips -- This book -- Interface with system architecture -- Shared memory networks in chip multiprocessors -- Impact of coherence protocol on network performance -- Coherence protocol requirements for the on-chip network -- Protocol-level network deadlock -- Impact of cache hierarchy implementation on network performance -- Home node and memory controller design issues -- Miss and transaction status holding registers -- Synthesized NoCs in MPSoCs -- The role of application characterization in NoC design -- Design requirements for on-chip network -- NoC synthesis -- NoC network interface standards -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Topology -- Metrics for comparing topologies -- Direct topologies: rings, meshes and Tori -- Indirect topologies: butterflies, Clos networks and fat trees -- Irregular topologies -- Splitting and merging -- Topology synthesis algorithm example -- Layout and implementation -- Concentrators -- Implication of abstract metrics on on-chip implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Routing -- Types of routing algorithms -- Deadlock avoidance -- Deterministic dimension-ordered routing -- Oblivious routing -- Adaptive routing -- Adaptive turn model routing -- Implementation -- Source routing -- Node table-based routing -- Combinational circuits -- Adaptive routing -- Routing on irregular topologies -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Flow control -- Messages, packets, flits and phits -- Message-based flow control -- Circuit switching -- Packet-based flow control -- Store and forward -- Cut-through -- Flit-based flow control -- Wormhole -- Virtual channels -- Deadlock-free flow control -- Escape VCs -- Buffer backpressure -- Implementation -- Buffer sizing for turnaround time -- Reverse signaling wires -- Flow control implementation in MPSoCs -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Router microarchitecture -- Virtual channel router microarchitecture -- Pipeline -- Pipeline implementation -- Pipeline optimizations -- Buffer organization -- Switch design -- Crossbar designs -- Crossbar speedup -- Crossbar slicing -- Allocators and arbiters -- Round-robin arbiter -- Matrix arbiter -- Separable allocator -- Wavefront allocator -- Allocator organization -- Implementation -- Router floorplanning -- Buffer implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Conclusions -- Gap between state-of-the-art and ideal -- Definition of ideal interconnect fabric -- Definition of state-of-the-art -- Network power-delay-throughput gap -- Key research challenges -- Low-power on-chip networks -- Beyond conventional interconnects -- Resilient on-chip networks -- NoC infrastructures -- On-chip network benchmarks -- On-chip networks conferences -- Bibliographic notes.
506	1		_aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510	0		_aCompendex
510	0		_aINSPEC
510	0		_aGoogle scholar
510	0		_aGoogle book search
520	3		_aWith the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
530			_aAlso available in print.
588			_aTitle from PDF t.p. (viewed on August 9, 2009).
650		0	_aNetworks on a chip.
690			_aInterconnection networks
690			_aTopology
690			_aRouting
690			_aFlow control
690			_aComputer architecture
690			_aMultiprocessor system on chip
700	1		_aPeh, Li-Shiuan.
730	0		_aSynthesis digital library of engineering and computer science.
830		0	_aSynthesis lectures on computer architecture, _x1935-3243 ; _v# 8.
856	4	2	_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6812992
999			_c561700 _d561700