000			05381nam a2200661 i 4500
001			6812806
003			IEEE
005			20200413152847.0
006			m eo d
007			cr cn |||m|||a
008			081011s2006 caua foab 000 0 eng d
020			_a1598291076 (electronic bk.)
020			_a9781598291070 (electronic bk.)
020			_a1598291068 (pbk.)
020			_a9781598291063 (pbk.)
024	7		_a10.2200/S00060ED1V01Y200610DCS006 _2doi
035			_a(OCoLC)73796751
035			_a(CaBNVSL)gtp00531446
040			_aCaBNVSL _cCaBNVSL _dCaBNVSL
050		4	_aTK7868.L6 _bR445 2006
082	0	4	_a621.395 _222
090			_a _bMoCl _e200610DCS006
100	1		_aReese, Robert B. _q(Robert Bryan), _d1958-
245	1	0	_aIntroduction to logic synthesis using Verilog HDL _h[electronic resource] / _cRobert B. Reese, Mitchell A. Thornton.
250			_a1st ed.
260			_aSan Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool Publishers, _cc2006.
300			_a1 electronic text (vii, 75 p. : ill.) : _bdigital file.
490	1		_aSynthesis lectures on digital circuits and systems, _x1932-3174 ; _v#6
538			_aMode of access: World Wide Web.
538			_aSystem requirements: Adobe Acrobat Reader.
500			_aPart of: Synthesis digital library of engineering and computer science.
500			_aSeries from website.
504			_aIncludes bibliographical references (p. 73).
505	0		_aDigital logic review with Verilog quickstart -- Learning objectives -- Logic synthesis introduction and motivation -- Combinational logic in Verilog -- Assign statements -- Always procedural blocks -- Combinational building blocks in Verilog -- Multibit/multiinput muxes, Verilog hierarchical design and bus notation -- Addition, subtraction -- Multiplication, division -- Shifting -- Tri-state logic -- Sequential logic in Verilog -- One-bit storage elements -- DFF chains -- Asynchronous versus synchronous inputs -- Registers, counters, and shift registers -- Event-driven simulation and Verilog -- Event-driven simulation basics -- Timing considerations -- Presynthesis versus postsynthesis simulation -- Blocking versus nonblocking assignments and synthesis -- Verilog coding guidelines -- Summary -- Synchronous sequential circuit design -- Learning objectives -- Sequential circuits -- Sequential circuit motivation -- Synchronizing signals: the clock -- Synchronous sequential circuit architectures -- Contents -- Models of finite state machines -- Basics of algorithmic state machine (ASM) charts -- The ASM chart model and an example controller -- The state diagram model -- State assignment -- Low-level models of controllers -- State equations -- State tables -- Controller circuit analysis -- Mealy and Moore machine conversion -- Mealy to Moore machine conversion -- Moore to Mealy conversion -- State machine equivalence -- Verilog descriptions of synchronous sequential circuits -- Example Verilog descriptions -- Verilog descriptions for the Mealy machine model of an example controller -- Verilog descriptions for the Moore machine model of an example controller -- Summary -- Biography.
506	1		_aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510	0		_aCompendex
510	0		_aINSPEC
510	0		_aGoogle scholar
510	0		_aGoogle book search
520			_aIntroduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.
530			_aAlso available in print.
588			_aTitle from PDF t.p. (viewed on October 11, 2008).
650		0	_aLogic design _xComputer programs.
650		0	_aVerilog (Computer hardware description language)
650		0	_aElectronic digital computers _xDesign and construction.
650		0	_aComputer hardware description languages.
690			_aVerilog.
690			_aDigital System Design.
690			_aDigital Logic Synthesis.
690			_aHDL (Hardware Description Language)
690			_aCombinational Logic.
690			_aSequential Logic.
700	1		_aThornton, Mitchell Aaron.
730	0		_aSynthesis digital library of engineering and computer science.
830		0	_aSynthesis lectures on digital circuits and systems ; _v#6.
856	4	2	_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6812806
856	4	0	_3Abstract with links to full text _uhttp://dx.doi.org/10.2200/S00060ED1V01Y200610DCS006
999			_c561547 _d561547