000			03989nam a2200661 i 4500
001			6812910
003			IEEE
005			20200413152847.0
006			m eo d
007			cr cn |||m|||a
008			081011s2008 caua foab 000 0 eng d
020			_a1598295306 (electronic bk.)
020			_a9781598295306 (electronic bk.)
020			_a1598295292 (pbk.)
020			_a9781598295290 (pbk.)
024	7		_a10.2200/S00087ED1V01Y200702DCS014 _2doi
035			_a(OCoLC)186658091
035			_a(CaBNVSL)gtp00531444
040			_aCaBNVSL _cCaBNVSL _dCaBNVSL
050		4	_aTK7888.3 _b.D284 2008
082	0	4	_a621.3916 _222
090			_a _bMoCl _e200702DCS014
100	1		_aDavis, Justin S., _d1975-
245	1	0	_aFinite state machine datapath design, optimization, and implementation _h[electronic resource] / _cJustin Davis, Robert Reese.
260			_aSan Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : _bMorgan & Claypool Publishers, _cc2008.
300			_a1 electronic text (ix, 113 p. : ill.) : _bdigital file.
490	1		_aSynthesis lectures on digital circuits and systems, _x1932-3174 ; _v#14
538			_aMode of access: World Wide Web.
538			_aSystem requirements: Adobe Acrobat Reader.
500			_aPart of: Synthesis digital library of engineering and computer science.
500			_aSeries from website.
504			_aIncludes bibliographical references.
505	0		_aChapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs.
506	1		_aAbstract freely available; full-text restricted to subscribers or individual document purchasers.
510	0		_aCompendex
510	0		_aINSPEC
510	0		_aGoogle scholar
510	0		_aGoogle book search
520			_aFinite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
530			_aAlso available in print.
588			_aTitle from PDF t.p. (viewed on October 11, 2008).
650		0	_aElectronic digital computers _xDesign and construction.
690			_aVerilog.
690			_aDatapath.
690			_aScheduling.
690			_aLatency.
690			_aThroughput.
690			_aTiming.
690			_aPipelining.
690			_aMemories.
690			_aFPGA.
690			_aFlowgraph.
700	1		_aReese, Robert B. _q(Robert Bryan), _d1958-
730	0		_aSynthesis digital library of engineering and computer science.
830		0	_aSynthesis lectures on digital circuits and systems ; _v#14.
856	4	2	_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/servlet/opac?bknumber=6812910
856	4	0	_3Abstract with links to full text _uhttp://dx.doi.org/10.2200/S00087ED1V01Y200702DCS014
999			_c561545 _d561545