000 03743nam a22004815i 4500
001 978-1-4020-6391-6
003 DE-He213
005 20161121231154.0
007 cr nn 008mamaa
008 100301s2007 ne | s |||| 0|eng d
020 _a9781402063916
_9978-1-4020-6391-6
024 7 _a10.1007/978-1-4020-6391-6
_2doi
050 4 _aTK1-9971
072 7 _aTJK
_2bicssc
072 7 _aTEC041000
_2bisacsh
082 0 4 _a621.382
_223
100 1 _aAbbasfar, Aliazam.
_eauthor.
245 1 0 _aTurbo-like Codes
_h[electronic resource] :
_bDesign for High Speed Decoding /
_cby Aliazam Abbasfar.
264 1 _aDordrecht :
_bSpringer Netherlands,
_c2007.
300 _aXVIII, 84 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aTurbo Concept -- High-speed Turbo Decoders -- Very Simple Turbo-like Codes -- High Speed Turbo-like Decoders.
520 _aThe advent of turbo codes has sparked tremendous research activities around the theoretical and practical aspects of turbo codes and turbo-like codes. The crucial novelty in these codes is the iterative decoding. Turbo-like Codes introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus of Turbo-like Codes is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps). In this book a novel high-speed turbo decoder is presented that exploits parallelization. Parallelism is achieved very efficiently by exploiting the flexibility of message-passing algorithm. It has been shown that very large speed gains can be achieved by this scheme while the efficiency is maintained reasonably high. Memory access, which poses a practical problem for the proposed parallel turbo decoder, is solved by introducing the conflict-free interleaver. The latency is further improved by designing a special kind of conflict-free interleaver. Furthermore, an algorithm to design such interleaver is presented. It is shown that the performance of turbo code is not sacrificed by using the interleaver with the proposed structure. Although turbo code has near Shannon-capacity performance and the proposed architecture for parallel turbo decoder provides a very efficient and highly regular hardware, the circuit is still very complex and demanding for very high-speed decoding. Therefore, the next step would be finding turbo-like codes that not only achieve excellent error correction capability, but also are very simple. As a result, a class of new Low-Density Parity-Check (LDPC) codes for different rates and block-sizes, called Accumulate-Repeat-Accumulate (ARA) codes, is presented. The performance of ARA codes is analyzed and shown that some ARA codes perform very close to random codes, which achieve Shannon limit.
650 0 _aEngineering.
650 0 _aCoding theory.
650 0 _aMicrowaves.
650 0 _aOptical engineering.
650 0 _aElectrical engineering.
650 1 4 _aEngineering.
650 2 4 _aCommunications Engineering, Networks.
650 2 4 _aMicrowaves, RF and Optical Engineering.
650 2 4 _aSignal, Image and Speech Processing.
650 2 4 _aCoding and Information Theory.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781402063909
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4020-6391-6
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c509627
_d509627