000			03616nam a22005055i 4500
001			978-1-4020-6195-0
003			DE-He213
005			20161121231154.0
007			cr nn 008mamaa
008			100301s2007 ne | s |||| 0|eng d
020			_a9781402061950 _9978-1-4020-6195-0
024	7		_a10.1007/978-1-4020-6195-0 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aHo, Tsung-Yi. _eauthor.
245	1	0	_aFull-Chip Nanometer Routing Techniques _h[electronic resource] / _cby Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_aXVIII, 102 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAnalog Circuits And Signal Processing Series
505	0		_aRouting Challenges for Nanometer Technology -- Multilevel Full-Chip Routing Considering Crosstalk And Performance -- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance -- Multilevel Full-Chip Routing For The X-Based Architecture -- Concluding Remarks And Future Work.
520			_aAs Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.
650		0	_aEngineering.
650		0	_aComputer-aided engineering.
650		0	_aElectronic circuits.
650		0	_aNanotechnology.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aNanotechnology.
700	1		_aChang, Yao-Wen. _eauthor.
700	1		_aChen, Sao-Jie. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402061943
830		0	_aAnalog Circuits And Signal Processing Series
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4020-6195-0
912			_aZDB-2-ENG
950			_aEngineering (Springer-11647)
999			_c509609 _d509609