000 04330nam a22004695i 4500
001 978-0-387-68739-1
003 DE-He213
005 20161121231150.0
007 cr nn 008mamaa
008 100301s2007 xxu| s |||| 0|eng d
020 _a9780387687391
_9978-0-387-68739-1
024 7 _a10.1007/978-0-387-68739-1
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
245 1 0 _aModern Circuit Placement
_h[electronic resource] :
_bBest Practices and Results /
_cedited by Gi-Joon Nam, Jason Cong.
264 1 _aBoston, MA :
_bSpringer US,
_c2007.
300 _aXX, 324 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSeries on Integrated Circuits and Systems,
_x1558-9412
505 0 _aBenchmarks -- ISPD 2005/2006 Placement Benchmarks -- Locality and Utilization in Placement Suboptimality -- Flat Placement Techniques -- DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective -- Kraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model -- Top-Down Partitioning-Based Techniques -- Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability -- Congestion Minimization in Modern Placement Circuits -- Multilevel Placement Techniques -- APlace: A High Quality, Large-Scale Analytical Placer -- FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm -- mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement -- mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control -- NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs -- Conclusion and Challenges.
520 _aModern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization. This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs. Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.
650 0 _aEngineering.
650 0 _aElectrical engineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aElectrical Engineering.
700 1 _aNam, Gi-Joon.
_eeditor.
700 1 _aCong, Jason.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387368375
830 0 _aSeries on Integrated Circuits and Systems,
_x1558-9412
856 4 0 _uhttp://dx.doi.org/10.1007/978-0-387-68739-1
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c509525
_d509525