000 03542nam a22004815i 4500
001 978-0-387-27038-8
003 DE-He213
005 20161121231107.0
007 cr nn 008mamaa
008 100301s2006 xxu| s |||| 0|eng d
020 _a9780387270388
_9978-0-387-27038-8
024 7 _a10.1007/b138536
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aSpear, Chris.
_eauthor.
245 1 0 _aSystemverilog for Verification
_h[electronic resource] :
_bA Guide to Learning the Testbench Language Features /
_cby Chris Spear.
264 1 _aBoston, MA :
_bSpringer US,
_c2006.
300 _aXXXIV, 302 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aVerification Guidelines -- Data Types -- Procedural Statements and Routines -- Basic OOP -- Connecting the Testbench and Design -- Randomization -- Threads and Interprocess Communication -- Advanced OOP and Guidelines -- Functional Coverage -- Advanced Interfaces.
520 _aBecome a SystemVerilog Expert! You can verify complex designs thoroughly and quickly if you start with the right tools. This book teaches you the SystemVerilog constructs for verification with over 300 examples. Learn proven techniques so you can build testbenches that automatically generate stimulus to catch those bugs. The SystemVerilog language contains hundreds of new features. This book shows you how to use the important ones to get your job done. You will learn how to use techniques such as * Interfaces and clocking blocks * Object oriented programming * Constrained random stimulus * Functional coverage * Logical assertions "SystemVerilog for Verification is a MUST prerequisite book for anyone involved in the creation of SystemVerilog testbenches, as standalone or in a framework like Synopsys VMM. I consider this work as a golden reference as it gets into the inner use of the language and provides excellent insights into practical coding styles. This book fills a needed void in explaining, in a very readable manner and with lots of examples and visuals, the key elements and applications of thelanguage for a verification methodology that supports constrained-random testing in a transaction-based methodology." Ben Cohen, Author/Consultant/Trainer, abv-sva.org http://abv-sva.org/ Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog's verification constructs. Chris is the author of the widely used File I/O PLI package for Verilog. Testbenches get more complex. You need this book to keep up! *** Includes over 300 examples *** Plus a foreword by Phil Moorby, creator of the Verilog language.
650 0 _aEngineering.
650 0 _aComputer hardware.
650 0 _aComputer-aided engineering.
650 0 _aElectrical engineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
650 2 4 _aComputer Hardware.
650 2 4 _aElectrical Engineering.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387270364
856 4 0 _uhttp://dx.doi.org/10.1007/b138536
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c508469
_d508469