000			04192nam a22005535i 4500
001			978-0-387-25556-9
003			DE-He213
005			20161121231107.0
007			cr nn 008mamaa
008			100301s2006 xxu| s |||| 0|eng d
020			_a9780387255569 _9978-0-387-25556-9
024	7		_a10.1007/b135575 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aBergeron, Janick. _eauthor.
245	1	0	_aVerification Methodology Manual for SystemVerilog _h[electronic resource] / _cby Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_aXVII, 503 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aVerification Planning -- Assertions -- Testbench Infrastructure -- Stimulus and Response -- Coverage-Driven Verification -- Assertions for Formal Tools -- System-Level Verification -- Processor Integration Verification.
520			_aFunctional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform. Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers. Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems. This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.
650		0	_aEngineering.
650		0	_aProgramming languages (Electronic computers).
650		0	_aComputer-aided engineering.
650		0	_aElectrical engineering.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aProgramming Languages, Compilers, Interpreters.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aElectrical Engineering.
700	1		_aCerny, Eduard. _eauthor.
700	1		_aHunter, Alan. _eauthor.
700	1		_aNightingale, Andrew. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387255385
856	4	0	_uhttp://dx.doi.org/10.1007/b135575
912			_aZDB-2-ENG
950			_aEngineering (Springer-11647)
999			_c508462 _d508462