000			03354nam a22004695i 4500
001			978-1-4020-8063-0
003			DE-He213
005			20161121231015.0
007			cr nn 008mamaa
008			100301s2005 xxu| s |||| 0|eng d
020			_a9781402080630 _9978-1-4020-8063-0
024	7		_a10.1007/b117054 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aGopalakrishnan, Prakash. _eauthor.
245	1	0	_aDirect Transistor-level Layout for Digital Blocks _h[electronic resource] / _cby Prakash Gopalakrishnan, Rob A. Rutenbar.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aIX, 125 p. 38 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aCircuit Structure and Clustering -- Global Placement -- Detailed Placement and Layout Results -- Timing-Driven Placement -- Conclusion.
520			_aCell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
650		0	_aEngineering.
650		0	_aComputer-aided engineering.
650		0	_aElectrical engineering.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectrical Engineering.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aRutenbar, Rob A. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402076657
856	4	0	_uhttp://dx.doi.org/10.1007/b117054
912			_aZDB-2-ENG
950			_aEngineering (Springer-11647)
999			_c507198 _d507198