000 04350nam a22005655i 4500
001 978-1-4020-7836-1
003 DE-He213
005 20161121231015.0
007 cr nn 008mamaa
008 100301s2005 xxu| s |||| 0|eng d
020 _a9781402078361
_9978-1-4020-7836-1
024 7 _a10.1007/b117241
_2doi
050 4 _aTJ212-225
072 7 _aTJFM
_2bicssc
072 7 _aTEC004000
_2bisacsh
082 0 4 _a629.8
_223
245 1 0 _aInterconnect-Centric Design for Advanced SoC and NoC
_h[electronic resource] /
_cedited by Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, Axel Jantsch.
264 1 _aBoston, MA :
_bSpringer US,
_c2005.
300 _aVIII, 454 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aPhysical and Electrical Issues -- System-on-Chip-Challenges in the Deep-Sub-Micron Era -- Wires as Interconnects -- Global Interconnect Analysis -- Design Methodologies for on-Chip Inductive Interconnect -- Clock Distribution for High Performance Designs -- Logical and Architectural Issues -- Error-Tolerant Interconnect Schemes -- Power Reduction Coding for Buses -- Bus Structures in Network-on-Chips -- From Buses to Networks -- Arbitration and Routing Schemes for on-Chip Packet Networks -- Design Methodology and Tools -- Self-Timed Approach for Noise Reduction in NoC Reduction in NoC -- Formal Communication Modeling and Refinement -- Network-Centric System-Level Model for Multiprocessor Soc Simulation -- Socket-Based Design Using Decoupled Interconnects -- Application Cases -- Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV -- A Brunch from the Coffee Table-Case Study in NoC Platform Design.
520 _aIn Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
650 0 _aEngineering.
650 0 _aSoftware engineering.
650 0 _aComputer-aided engineering.
650 0 _aSystem theory.
650 0 _aControl engineering.
650 0 _aElectrical engineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aControl.
650 2 4 _aCircuits and Systems.
650 2 4 _aElectrical Engineering.
650 2 4 _aSoftware Engineering/Programming and Operating Systems.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
650 2 4 _aSystems Theory, Control.
700 1 _aNurmi, Jari.
_eeditor.
700 1 _aTenhunen, Hannu.
_eeditor.
700 1 _aIsoaho, Jouni.
_eeditor.
700 1 _aJantsch, Axel.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781402078354
856 4 0 _uhttp://dx.doi.org/10.1007/b117241
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c507195
_d507195