000			03430nam a22005535i 4500
001			978-0-387-25624-5
003			DE-He213
005			20161121231012.0
007			cr nn 008mamaa
008			100301s2005 xxu| s |||| 0|eng d
020			_a9780387256245 _9978-0-387-25624-5
024	7		_a10.1007/b135763 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aLarsson, Erik. _eauthor.
245	1	0	_aIntroduction to Advanced System-on-Chip Test Design and Optimization _h[electronic resource] / _cby Erik Larsson.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aXX, 388 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aFrontiers in Electronic Testing, _x0929-1296 ; _v29
505	0		_aTesting Concepts -- Design Flow -- Design for Test -- Boundary Scan -- SOC Design for Testability -- System Modeling -- Test Conflicts -- Test Power Dissipation -- Test Access Mechanism -- Test Scheduling -- SOC Test Applications -- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling -- An Integrated Framework for the Design and Optimization of SOC Test Solutions -- Efficient Test Solutions for Core-Based Designs -- Core Selection in the SOC Test Design-Flow -- Defect-Aware Test Scheduling -- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.
520			_aSOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
650		0	_aEngineering.
650		0	_aEngineering design.
650		0	_aElectrical engineering.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650		0	_aOptical materials.
650		0	_aElectronic materials.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectrical Engineering.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aEngineering Design.
650	2	4	_aOptical and Electronic Materials.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402032073
830		0	_aFrontiers in Electronic Testing, _x0929-1296 ; _v29
856	4	0	_uhttp://dx.doi.org/10.1007/b135763
912			_aZDB-2-ENG
950			_aEngineering (Springer-11647)
999			_c507118 _d507118