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001 978-0-387-74909-9
003 DE-He213
005 20161121230712.0
007 cr nn 008mamaa
008 100301s2008 xxu| s |||| 0|eng d
020 _a9780387749099
_9978-0-387-74909-9
024 7 _a10.1007/978-0-387-74909-9
_2doi
050 4 _aTK5105.5-5105.9
072 7 _aUKN
_2bicssc
072 7 _aCOM075000
_2bisacsh
082 0 4 _a004.6
_223
245 1 0 _aVLSI-SoC: Research Trends in VLSI and Systems on Chip
_h[electronic resource] :
_bFourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France /
_cedited by Giovanni De Micheli, Salvador Mir, Ricardo Reis.
264 1 _aBoston, MA :
_bSpringer US,
_c2008.
300 _aX, 398 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aIFIP International Federation for Information Processing,
_x1868-4238 ;
_v249
505 0 _aArchitectures for High Dynamic Range, High Speed Image Sensor Readout Circuits -- Oversampled Time Estimation Techniques for Precision Photonic Detectors -- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices -- Electronic Detection of DNA Adsorption and Hybridization -- Probabilistic amp; Statistical Design—the Wave of the Future -- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs -- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design -- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design -- Soft Error Resilient System Design through Error Correction -- Library Compatible Variational Delay Computation -- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures -- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots -- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation -- Logic Synthesis of EXOR Projected Sum of Products -- A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits -- CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization -- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation -- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies -- Designing Routing and Message-Dependent Deadlock Free Networks on Chips -- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model -- Human++: Emerging Technology for Body Area Networks.
520 _aInternational Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springer.com. For more information about IFIP, please visit www.ifip.org.
650 0 _aComputer science.
650 0 _aMicroprocessors.
650 0 _aComputer communication systems.
650 1 4 _aComputer Science.
650 2 4 _aComputer Communication Networks.
650 2 4 _aProcessor Architectures.
700 1 _aMicheli, Giovanni De.
_eeditor.
700 1 _aMir, Salvador.
_eeditor.
700 1 _aReis, Ricardo.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387749082
830 0 _aIFIP International Federation for Information Processing,
_x1868-4238 ;
_v249
856 4 0 _uhttp://dx.doi.org/10.1007/978-0-387-74909-9
912 _aZDB-2-SCS
950 _aComputer Science (Springer-11645)
999 _c502708
_d502708