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005 20161121230610.0
007 cr nn 008mamaa
008 100301s2007 xxu| s |||| 0|eng d
020 _a9780387736617
_9978-0-387-73661-7
024 7 _a10.1007/978-0-387-73661-7
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
245 1 0 _aVlsi-Soc: From Systems To Silicon
_h[electronic resource] :
_bProceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia /
_cedited by Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer.
264 1 _aBoston, MA :
_bSpringer US,
_c2007.
300 _aX, 344 p. 176 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aIFIP International Federation for Information Proc,
_x1868-4238 ;
_v240
505 0 _aMolecular Electronics – Devices and Circuits Technology -- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals -- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures -- Defragmentation Algorithms for Partially Reconfigurable Hardware -- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits -- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System -- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms -- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis -- Issues in Model Reduction of Power Grids -- A Traffic Injection Methodology with Support for System-Level Synchronization -- Pareto Points in SRAM Design Using the Sleepy Stack Approach -- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs -- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping -- A Novel MicroPhotonic Structure for Optical Header Recognition -- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint -- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS -- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles -- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction -- Exact BDD Minimization for Path-Related Objective Functions -- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks -- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
520 _aInternational Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springer.com. For more information about IFIP, please visit www.ifip.org.
650 0 _aEngineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
700 1 _aReis, Ricardo.
_eeditor.
700 1 _aOsseiran, Adam.
_eeditor.
700 1 _aPfleiderer, Hans-Joerg.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387736600
830 0 _aIFIP International Federation for Information Proc,
_x1868-4238 ;
_v240
856 4 0 _uhttp://dx.doi.org/10.1007/978-0-387-73661-7
912 _aZDB-2-SCS
950 _aComputer Science (Springer-11645)
999 _c501162
_d501162