000 03374nam a22004575i 4500
001 978-1-4020-8652-6
003 DE-He213
005 20161121230536.0
007 cr nn 008mamaa
008 100301s2008 ne | s |||| 0|eng d
020 _a9781402086526
_9978-1-4020-8652-6
024 7 _a10.1007/978-1-4020-8652-6
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aWieferink, Andreas.
_eauthor.
245 1 0 _aRetargetable Processor System Integration into Multi-Processor System-on-Chip Platforms
_h[electronic resource] /
_cby Andreas Wieferink, Heinrich Meyr, Rainer Leupers.
264 1 _aDordrecht :
_bSpringer Netherlands,
_c2008.
300 _aXIV, 162 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aSOC Design Methodologies -- Communication Modeling -- Processor Modeling -- Processor System Integration -- Successive Top-Down Refinement Flow -- Automatic Retargetability -- Debugging and Profiling -- Case Study -- Summary.
520 _aThe ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWare’s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores. In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms. The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.
650 0 _aEngineering.
650 0 _aSpecial purpose computers.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aSpecial Purpose and Application-Based Systems.
700 1 _aMeyr, Heinrich.
_eauthor.
700 1 _aLeupers, Rainer.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781402085741
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4020-8652-6
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c500325
_d500325