000 04532nam a22005055i 4500
001 978-1-4020-8297-9
003 DE-He213
005 20161121230536.0
007 cr nn 008mamaa
008 100301s2008 ne | s |||| 0|eng d
020 _a9781402082979
_9978-1-4020-8297-9
024 7 _a10.1007/978-1-4020-8297-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
245 1 0 _aEmbedded Systems Specification and Design Languages
_h[electronic resource] :
_bSelected contributions from FDL’07 /
_cedited by Eugenio Villar.
264 1 _aDordrecht :
_bSpringer Netherlands,
_c2008.
300 _aIX, 275 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v10
505 0 _aC/C++ Based System Design -- How Different Are Esterel and SystemC -- Timed Asynchronous Circuits Modeling and Validation Using SystemC -- On Construction of Cycle Approximate Bus TLMs -- Combinatorial Dependencies in Transaction Level Models -- An Integrated SystemC Debugging Environment -- Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques -- SystemC-Based Simulation of the MICAS Architecture -- Analog, Mixed-Signal, and Heterogeneous System Design -- Heterogeneous Specification with HetSC and SystemC-AMS: Widening the Support of MoCs in SystemC -- An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations -- Mixed-Level Modeling Using Configurable MOS Transistor Models -- UML-Based System Specification and Design -- Modeling AADL Data Communications with UML MARTE -- Software Real-Time Resource Modeling -- Model Transformations from a Data Parallel Formalism Towards Synchronous Languages -- UML and SystemC – A Comparison and Mapping Rules for Automatic Code Generation -- An Enhanced SystemC UML Profile for Modeling at Transaction-Level -- SC2 StateCharts to SystemC: Automatic Executable Models Generation -- Formalisms for Property-Driven Design -- Asynchronous On-Line Monitoring of Logical and Temporal Assertions -- Transactor-Based Formal Verification of Real-Time Embedded Systems -- A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set.
520 _aFDL is the most important European and, probably, worldwide forum to present research results, to exchange experiences, and to learn about new trends in the application of specification and design languages and the associated design and modeling methods and tools for complex, heterogeneous HW/SW embedded systems. FDL’07 was the tenth of a series of successful events held all around Europe. FDL’07 was held in Barcelona, the capital city of Catalonia, Spain. The high number of submissions to the conference this year allowed the Program Committee to prepare a high quality conference program. Embedded Systems Specification and Design Languages includes a selection of the most relevant contributions based on the review made by the program committee members and the quality of the contents of the presentation at the conference. In many cases, the authors have improved the original content with additional technical information. The papers cover the most important aspects in system modeling and specification, an essential area in Embedded Systems design. The objective of Embedded Systems Specification and Design Languages is to serve as a reference text for researchers and designers interested in the extension and improvement of the application of design and verification languages in the area of Embedded Systems.
650 0 _aEngineering.
650 0 _aComputer hardware.
650 0 _aSpecial purpose computers.
650 0 _aSoftware engineering.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aComputer Hardware.
650 2 4 _aSpecial Purpose and Application-Based Systems.
650 2 4 _aSoftware Engineering/Programming and Operating Systems.
700 1 _aVillar, Eugenio.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781402082962
830 0 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v10
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4020-8297-9
912 _aZDB-2-ENG
950 _aEngineering (Springer-11647)
999 _c500301
_d500301