000 00510pam a2200157a 44500
008 160408b2011 xxu||||| |||| 00| 0 eng d
020 _a9781441975478
040 _aIIT, Kanpur
082 _a621.3815
_bN227d
100 _aNavabi, Zainalabedin
245 1 _aDigital system test and testable design
_busing HDL models and architectures
_cZainalabedin Navabi
260 _aNew York
_bSpringer
_c2011
300 _axxiii, 435p
650 _aSyetems on a chip
997 _aA171275 C
999 _c368858
_d368858