000 00590pam a2200205a 44500
008 160408b1990 xxu||||| |||| 00| 0 eng d
020 _a0962748803
082 _a003
_bSt45d
100 _aSternheim, Eliezer
245 1 _aDIGITAL DESIGN WITH VERILOG HDL
260 _aCupertino
_bAutomata Pub.
_c1990
300 _aviii,214
440 _aDesign Automation Series
_v
500 _aFormerly Titled : Hardware Modeling With Verilog Hdl
650 _aHardware Discription Language
650 _aSystem Analysis
700 _aTrivedi, Yatin
964 _gCIRC
997 _aA112998 C
999 _c325881
_d325881