Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.

Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references and index.

1. Introduction -- 1.1 Memory wall -- 1.2 Traditional semiconductor memory -- 1.2.1 Overview -- 1.2.2 Nano-scale limitations -- 1.3 Non-volatile spintronic memory -- 1.3.1 Basic magnetization process -- 1.3.2 Magnetization damping -- 1.3.3 Spin-transfer torque -- 1.3.4 Magnetization dynamics -- 1.3.5 Domain wall propagation -- 1.4 Traditional memory architecture -- 1.5 Non-volatile in-memory computing architecture -- 1.6 References --

2. Non-volatile spintronic device and circuit -- 2.1 SPICE formulation with new nano-scale NVM devices -- 2.1.1 Traditional modified nodal analysis -- 2.1.2 New MNA with non-volatile state variables -- 2.2 STT-MTJ device and model -- 2.2.1 STT-MTJ -- 2.2.2 STT-RAM -- 2.2.3 Topological insulator -- 2.3 Domain wall device and model -- 2.3.1 Magnetization reversal -- 2.3.2 MTJ resistance -- 2.3.3 Domain wall propagation -- 2.3.4 Circular domain wall nanowire -- 2.4 Spintronic storage -- 2.4.1 Spintronic memory -- 2.4.2 Spintronic readout -- 2.5 Spintronic logic -- 2.5.1 XOR -- 2.5.2 Adder -- 2.5.3 Multiplier -- 2.5.4 LUT -- 2.6 Spintronic interconnect -- 2.6.1 Coding-based interconnect -- 2.6.2 Domain wall-based encoder/decoder -- 2.6.3 Performance evaluation -- 2.7 References --

3. In-memory data encryption -- 3.1 In-memory advanced encryption standard -- 3.1.1 Fundamental of AES -- 3.1.2 Domain wall nanowire-based AES computing -- 3.1.3 Pipelined AES by domain wall nanowire -- 3.1.4 Performance evaluation -- 3.2 Domain wall-based SIMON block cipher -- 3.2.1 Fundamental of SIMON block cipher -- 3.2.2 Hardware stages -- 3.2.3 Round counter -- 3.2.4 Control signals -- 3.2.5 Key expansion -- 3.2.6 Encryption -- 3.2.7 Performance evaluation -- 3.3 References --

4. In-memory data analytics -- 4.1 In-memory machine learning -- 4.1.1 Extreme learning machine -- 4.1.2 MapReduce-based matrix multiplication -- 4.1.3 Domain wall-based hardware mapping -- 4.1.4 Performance evaluation -- 4.2 In-memory face recognition -- 4.2.1 Energy-efficient STT-MRAM with Spare-represented data -- 4.2.2 QoS-aware adaptive current scaling -- 4.2.3 STT-RAM based hardware mapping -- 4.2.4 Performance evaluation -- 4.3 References -- Authors' biographies.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since the main bottleneck is from memory, we aim to develop an energy-efficient in-memory computing platform in this book. First, the models of spin-transfer torque magnetic tunnel junction and racetrack memory are presented. Next, we show that the spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect. As a result, by utilizing spintronics, in-memory-based computing has been applied for data encryption and machine learning. The implementations of in-memory AES, Simon cipher, as well as interconnect are explained in details. In addition, in-memory-based machine learning and face recognition are also illustrated in this book.

Also available in print.

Title from PDF title page (viewed on December 5, 2016).