Designing asynchronous circuits using NULL convention logic (NCL)
By: Smith, Scott C.
Contributor(s): Di, Jia.
Material type:
BookSeries: Synthesis lectures on digital circuits and systems: # 23.Publisher: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009Description: 1 electronic text (x, 86 p. : ill.) : digital file.ISBN: 9781598299823 (electronic bk.).Uniform titles: Synthesis digital library of engineering and computer science. Subject(s): Asynchronous circuits -- Design and construction | Combinational circuits | Sequential circuits | Logic, Symbolic and mathematical | Logic design | Computer engineering | Digital design | Asynchronous logic | Delay-insensitive logic | Combinational logic | Sequential logic | NULL Convention Logic | NCL | Input-completeness | Observability | Dual-rail | Quad-rail | Pipelining | Embedded registration | Early completion | NULL cycle reduction | Wavefront steering | MTCMOSDDC classification: 621.3815 Online resources: Abstract with links to resource Also available in print.| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
E books
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PK Kelkar Library, IIT Kanpur | Available | EBKE195 |
Mode of access: World Wide Web.
System requirements: Adobe Acrobat reader.
Part of: Synthesis digital library of engineering and computer science.
Series from website.
Includes bibliographical references.
Introduction to asynchronous logic -- Overview of NULL convention logic (NCL) -- NCL system framework and fundamental components -- Transistor-level NCL gate design -- Combinational NCL circuit design -- Input-completeness and observability -- Dual-rail NCL design -- Quad-rail NCL design -- Sequential NCL circuit design -- NCL implementation of Mealy and Moore machines -- NCL implementation of algorithmic state machines -- NCL throughput optimization -- Pipelining -- Embedded registration -- Early completion -- NULL cycle reduction -- Low-power NCL design -- Wavefront steering -- Multi-threshold CMOS (MTCMOS) for NCL (MTNCL) -- MTCMOS for synchronous circuits -- Implementing MTCMOS in NCL circuits -- Comprehensive NCL design example.
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
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Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power.
Also available in print.
Title from PDF t.p. (viewed on August 9, 2009).
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