Concurrent fault simulation of Mos logic circuits
By: Rajendra Prasad.
Material type:
BookPublisher: Kanput IIT Kanpur 1987Description: 83p.
| Item type | Current location | Collection | Call number | url | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|---|
Thesis
|
PK Kelkar Library, IIT Kanpur | Reference | 629.2 H365a2 (Browse shelf) | Book Request | Not for loan | A98929 |
Total holds: 0
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