Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
By: Henzler, Stephan [author.].
Contributor(s): SpringerLink (Online service).
Material type:
BookSeries: Advanced Microelectronics: 25Publisher: Dordrecht : Springer Netherlands, 2007.Description: XVI, 186 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781402050817.Subject(s): Engineering | Energy systems | Solid state physics | Electric power production | Spectroscopy | Microscopy | Electrical engineering | Electronic circuits | Engineering | Circuits and Systems | Energy Technology | Electrical Engineering | Solid State Physics | Spectroscopy and Microscopy | Energy SystemsDDC classification: 621.3815 Online resources: Click here to access online | Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
E books
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PK Kelkar Library, IIT Kanpur | Available | EBK9844 |
TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN -- LOGIC WITH MULTIPLE SUPPLY VOLTAGES -- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES -- FORCING OF TRANSISTOR STACKS -- POWER GATING -- CONCLUSION.
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.
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