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Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

By: Kogel, Tim [author.].
Contributor(s): Leupers, Rainer [author.] | Meyr, Heinrich [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Dordrecht : Springer Netherlands, 2006.Description: XIV, 186 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781402048265.Subject(s): Engineering | Special purpose computers | Software engineering | Computer simulation | Computer-aided engineering | Electronics | Microelectronics | Electronic circuits | Engineering | Circuits and Systems | Software Engineering/Programming and Operating Systems | Electronics and Microelectronics, Instrumentation | Simulation and Modeling | Special Purpose and Application-Based Systems | Computer-Aided Engineering (CAD, CAE) and DesignDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Foreword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index.
In: Springer eBooksSummary: We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.
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Item type Current location Call number Status Date due Barcode Item holds
E books E books PK Kelkar Library, IIT Kanpur
Available EBK8874
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Foreword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index.

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

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