Direct Transistor-level Layout for Digital Blocks
By: Gopalakrishnan, Prakash [author.].
Contributor(s): Rutenbar, Rob A [author.] | SpringerLink (Online service).
Material type:
BookPublisher: Boston, MA : Springer US, 2005.Description: IX, 125 p. 38 illus. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781402080630.Subject(s): Engineering | Computer-aided engineering | Electrical engineering | Electronic circuits | Engineering | Circuits and Systems | Electrical Engineering | Computer-Aided Engineering (CAD, CAE) and DesignDDC classification: 621.3815 Online resources: Click here to access online | Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|
E books
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PK Kelkar Library, IIT Kanpur | Available | EBK7485 |
Circuit Structure and Clustering -- Global Placement -- Detailed Placement and Layout Results -- Timing-Driven Placement -- Conclusion.
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
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