System verilog for verification : a guide to learning the testbench language features
By: Spear, Chris.
Material type:
BookPublisher: New York Springer 2008Edition: 2nd.Description: xxxvi, 429p.ISBN: 9780387765297.Subject(s): Integrated circuitsDDC classification: 621.392 | Sp31s2
| Item type | Current location | Collection | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|
Books
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PK Kelkar Library, IIT Kanpur | General Stacks | 621.392 Sp31s2 (Browse shelf) | Available | A164962 |
Total holds: 0
Browsing PK Kelkar Library, IIT Kanpur Shelves , Collection code: General Stacks Close shelf browser
| 621.392 R743D DIGITAL SYSTEMS DESIGN USING VHDL | 621.392 R952c Channel codes | 621.392 SA31V VHDL AND FPLDS IN DIGITAL SYSTEMS DESIGN, PROTOTYPING AND CUSTOMIZATION | 621.392 Sp31s2 System verilog for verification | 621.392 SU84S2 SYSTEMVERILOG FOR DESIGN | 621.392 T361V4 VERILOG HARDWARE DESCRIPTION LANGUAGE | 621.392 T362V2 VERILOG HARDWARE DESCRIPTION LANGUAGE |
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