Verification techniques for system-level design
By: Fujita, Masahiro, Ghosh, Indradeep.
Contributor(s): Prasad, Mukul.
Material type:
BookSeries: The Morgan Kaufmann Series In Systems On Silicon. Publisher: Amsterdam Elsevier 2008Description: viii, 240p.ISBN: 9780123706164.Subject(s): System On A Chip -- Testing. 2.Integrated Circuits -- Verification. 3.Formal Method (Computer Science)DDC classification: 621.3815 | F955v
| Item type | Current location | Collection | Call number | Status | Date due | Barcode | Item holds |
|---|---|---|---|---|---|---|---|
Books
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PK Kelkar Library, IIT Kanpur | General Stacks | 621.3815 F955v (Browse shelf) | Available | A160090 |
Total holds: 0
Browsing PK Kelkar Library, IIT Kanpur Shelves , Collection code: General Stacks Close shelf browser
| 621.3815 F556t TRANSISTOR CIRCUIT ANALYSIS AND DESIGN | 621.3815 F582a Analog design and simulation using OrCAD capture and PSpice | 621.3815 F811c Creating Asseration-Based IP | 621.3815 F955v Verification techniques for system-level design | 621.3815 G181L LABORATORY MANUAL ON DIGITAL DESIGN USING | 621.3815 G341c CMOS capacitive sensors for lab-on-chip applications | 621.3815 G755c Carbon nanotube-polymer composites |
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