Timing channels in cryptography [Perpetual access] (Record no. 565145)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01925 a2200241 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319123707 |
| 040 ## - CATALOGING SOURCE | |
| Transcribing agency | IIT Kanpur |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.82 |
| Item number | R241t |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Rebeiro, Chester |
| 245 ## - TITLE STATEMENT | |
| Title | Timing channels in cryptography [Perpetual access] |
| Remainder of title | a micro-architectural perspective |
| Statement of responsibility, etc | Chester Rebeiro, Debdeep Mukhopadhyay and Sarani Bhattacharya |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher | Springer |
| Year of publication | 2015 |
| Place of publication | Switzerland |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xvii, 152p |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book deals with timing attacks on software implementations of encryption algorithms. It describes and analyzes various unintended covert timing channels that are formed when ciphers are executed in microprocessors. Modern superscalar microprocessors are considered, which are enabled with features such as multi-threaded, pipelined, parallel, speculative, and out-of-order execution. Various timing attack algorithms are described and analyzed for block ciphers as well as public-key ciphers. The interplay between the cipher implementation, system architecture, and the attack's success is analyzed. Further hardware and software countermeasures are discussed with the aim of illustrating methods to build systems that can protect against these attacks. Discusses various timing attack algorithms in detail allowing readers to reconstruct the attack. Provides several experimental results to support the theoretical analysis provided in the book. Analyzes information leakage from cache memories and branch prediction units in the processor. Examines information leakage models that would help quantify leakage in a covert timing channels. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Data encryption (Computer science) |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Data structures (Computer science) |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Cryptography |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Mukhopadhyay, Debdeep |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Bhattacharya, Sarani |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://link.springer.com/book/10.1007%2F978-3-319-12370-7#about |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | E books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Date acquired | Source of acquisition | Cost, normal purchase price | Full call number | Accession Number | Cost, replacement price | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Electronic Resources | PK Kelkar Library, IIT Kanpur | PK Kelkar Library, IIT Kanpur | 2022-04-28 | 88 | 16536.06 | 005.82 R241t | EBK10743 | 16536.06 | E books |